PIC18F25K42-E/ML - 8-Bit 64MHz 32KB Flash MCU | Microchip
MPN: PIC18F25K42-E/ML ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.95 | $2.95 |
| 10 | $2.66 | $26.60 |
| 100 | $2.31 | $231.00 |
| 500 | $2.04 | $1,020.00 |
| 1,000 | $1.79 | $1,790.00 |
PIC18F25K42-E/ML Overview
What is a PIC18 microcontroller? A PIC18 is an 8-bit Harvard-architecture RISC MCU from Microchip's PIC family. The PIC18 sub-family adds 16-bit instruction words, hardware multiply, C-compiler friendly architecture, and rich peripheral integration, sitting within the broader hierarchy: PIC18 -> 8-bit PIC -> PIC microcontroller -> microcontroller -> embedded processor -> semiconductor. K42-series parts in particular add Functional Safety features (windowed WDT, CRC/Scan, Memory Partitioning) targeted at IEC 61508 / SIL-aware designs.
Key features include a 12-bit ADC2 with Computation (ADC2) for automated capacitive voltage-divider touch sensing, DMA between peripherals and RAM, 5-bit DAC, 4 CLCs for hardware glue logic, Configurable Logic Cells, Zero-Cross Detect, Complementary Waveform Generator, High/Low-Timing modules, Windowed Watchdog Timer, and PPS (Peripheral Pin Select) for flexible signal routing. The XLP nanoWatt XLP sleep currents (under 50 nA typical in Sleep with RAM retention on the L-variant) make it attractive for battery or energy-harvesting endpoints.
The K42 architecture executes 16-bit instructions from Flash with a 31-level hardware stack and runs most instructions in a single 64 MHz clock cycle, while peripheral operation continues in Doze/Idle. Vectored interrupt handling provides fixed deterministic latency, and the System Bus Arbiter resolves DMA-vs-CPU conflicts automatically. The 12-bit ADC2 with post-processing computes averaging, oversampling and threshold compare in hardware, offloading the CPU for sensor-conditioning loops.
Typical applications include low-power IoT sensor nodes, capacitive-touch user interfaces, automotive body and HVAC controls, consumer appliances with displays, industrial sensor signal conditioning, USB-less serial bridge products, and functional-safety sensor endpoints. The wide 1.8 V - 5.5 V VDD range and -40C to +125C operation suit outdoor, industrial, and automotive under-hood zones.
A practical design tip: when migrating from the K40 or K22 families to the K42, re-verify the PPS assignments and the new 12-bit ADC2 trigger sources - the K42 introduces new trigger sources and removes some that existed on K40. Always program the WDT using the WWDT-conf (FCMEN, IESO, RTC) configuration words early in development so an unintended reset does not corrupt EEPROM writes.
This page synthesises distributor pricing, drop-in same-package alternatives (K40, K42 -I / -MV siblings, F-series 28-QFN PIC18s) and practical design guidance not all packaged together in the manufacturer datasheet, helping engineers evaluate fit and source the right part faster.
Drop-in alternatives for PIC18F25K42-E/ML — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PIC18F25K42-E/ML (same form factor and footprint) — differing in Package, Comparators, Operating Temperature, RAM, EEPROM.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PIC18F25K42-I/ML
✅ Drop-In📋 Reference alternative (not in catalog)
PIC18F24K42-E/ML
✅ Drop-In✓ In Stock
$1.68 / Unit
View Datasheet →PIC18F25K42-E/MV
✅ Drop-In📋 Reference alternative (not in catalog)
PIC18F25K40-I/ML
✅ Drop-In📋 Reference alternative (not in catalog)
PIC18F25K40T-I/ML
✅ Drop-In✓ In Stock
$1.85 / Unit
View Datasheet →PIC18F25K20-E/ML
✅ Drop-In✓ In Stock
$2.95 / Unit
View Datasheet →PIC18F25K42-E/ML Maximum Ratings & Electrical Characteristics
| No specifications available |
PIC18F25K42-E/ML Pin Configuration
| Pin 1 | RA2/AN2/T0CKI/CLC4IN0/CCP3/PWM3 — PORTA I/O pin 2; analog channel 2; Timer0 clock input; CLC4 input 0; CCP3/PWM3 output |
| Pin 2 | RA3/AN3/T5G/CLKR/CLC1IN0 — PORTA I/O pin 3; analog channel 3; Timer5 gate input; clock reference output; CLC1 input |
| Pin 3 | RA4/AN4/T1G/CLKOUT — PORTA I/O pin 4; analog channel 4; Timer1 gate; system clock output |
| Pin 4 | RA5/AN5/DAC1OUT2 — PORTA I/O pin 5; analog channel 5; DAC1 output 2 |
| Pin 5 | VDD — Positive supply, 2.3 V to 5.5 V (-E/ML F-suffix) |
| Pin 6 | VSS — Ground |
| Pin 7 | RA7/OSC1/CLKIN — PORTA I/O 7; primary oscillator input; external clock input |
| Pin 8 | RB0/AN12/INT0/CLC8IN0/PWM4 — PORTB I/O 0; analog 12; external INT0; CLC8 input; PWM4 output |
| Pin 9 | RB1/AN10/INT1/CRX1/CCP4 — PORTB I/O 1; analog 10; external INT1; CAN RX; CCP4 output |
| Pin 10 | RB2/AN8/INT2/CTX1/CCP5 — PORTB I/O 2; analog 8; external INT2; CAN TX; CCP5 output |
| Pin 11 | RB3/AN9/INT3/CCP6 — PORTB I/O 3; analog 9; external INT3; CCP6 output |
| Pin 12 | RB4/AN11/IOC — PORTB I/O 4; analog 11; interrupt-on-change wake |
| Pin 13 | RB5/AN13/IOC — PORTB I/O 5; analog 13; interrupt-on-change wake |
| Pin 14 | RB6/ICSPCLK/IOC — PORTB I/O 6; ICD/ICSP clock; interrupt-on-change wake |
| Pin 15 | RB7/ICSPDAT/IOC — PORTB I/O 7; ICD/ICSP data; interrupt-on-change wake |
| Pin 16 | RC0/SOSCO/AN16 — PORTC I/O 0; secondary oscillator output; analog 16 |
| Pin 17 | RC1/SOSCI/AN17 — PORTC I/O 1; secondary oscillator input; analog 17 |
| Pin 18 | RC2/AN18/DAC1OUT1 — PORTC I/O 2; analog 18; DAC1 output 1 |
| Pin 19 | RC3/AN19/DAC2OUT1 — PORTC I/O 3; analog 19; DAC2 output 1 |
| Pin 20 | RC4/AN20 — PORTC I/O 4; analog 20 |
| Pin 21 | RC5/AN21 — PORTC I/O 5; analog 21 |
| Pin 22 | RC6/AN22/CCP9 — PORTC I/O 6; analog 22; CCP9 output |
| Pin 23 | RC7/AN23/CCP10 — PORTC I/O 7; analog 23; CCP10 output |
| Pin 24 | RE0/AN5 — PORTE I/O 0; analog 5 |
| Pin 25 | RE1/AN6 — PORTE I/O 1; analog 6 |
| Pin 26 | RE2/AN7 — PORTE I/O 2; analog 7 |
| Pin 27 | RE3/MCLR/VPP — PORTE I/O 3; master clear reset (input); programming voltage |
| Pin 28 | RA1/AN1/RA0(Alt) — PORTA I/O 1; analog channel 1 |
| Pin EP | EP-VSS — Exposed thermal pad, internally bonded to VSS; must be soldered to PCB ground pour for thermal dissipation |
Typical Applications
PIC18F25K42-E/ML is suitable for 7 applications: Low-Power IoT Sensor Node, Capacitive Touch User Interface, Automotive Body and HVAC Control, Industrial Sensor Signal Conditioning, Appliance and White Goods Display Controller, Energy Harvesting / Solar Trickle-Charge Endpoint, Functional Safety Sensor / SIL-Aware Endpoint.
Low-Power IoT Sensor Node
The PIC18F25K42-E/ML is ideal for battery-powered IoT sensor nodes thanks to its eXtreme Low-Power XLP nanoWatt sleep currents (sub-50 nA in Sleep with RAM retention), 2.3 V - 5.5 V VDD range compatible with LiSOCl2 primary cells, and integrated peripherals that wake the CPU only on real events. The 12-bit ADC2 with Computation (ADC2) digitises thermistor, photodiode or 4-20 mA sensor signals without the CPU running, DMA transfers result to RAM, and interrupt wakes the MCU for transmission. Typical architecture: BME280 sensor on I2C, RTC-driven periodic wake every 60 s, AES encryption in firmware, BLE module triggered through a CLC state machine. The on-board WWDT and Functional Safety (FuSa) blocks let a designer add diagnostics for IEC 61508-aware deployments such as gas detection. Compared with a discrete AFE, the integrated ADC2 reduces BOM by 30 percent.
Recommended
Capacitive Touch User Interface
The PIC18F25K42-E/ML's 12-bit ADC2 with Computation (ADC2) implements Capacitive Voltage Divider (CVD) touch detection in hardware, removing the need for an external touch controller. Each wake cycle performs a hardware-averaged conversion through the ADC2 accumulator, transfers it via DMA to RAM, and a small state machine compares it against the calibrated baseline - all without CPU intervention. This keeps total touch-scan current under 20 uA per scan cycle. Typical architecture: 12-button matrix with mTouch CVD scan every 10 ms, 4-segment LED drive via the CWG module, slide/wheel implemented in CLC hardware. The 4 CLCs replace external AND/OR glue logic, freeing board space. Drop-in K25 PIC18F25K42 fits directly on white-goods, doorbells, and kitchen-appliance touchpads rated to +125 C. Migrate from mTouch-tuned PIC16 or PIC18F24K42 designs by enabling ADC2 instead of the older 10-bit ADC2.
Recommended
Automotive Body and HVAC Control
The PIC18F25K42-E/ML's -40C to +125C extended temperature grade plus Windowed Watchdog Timer (WWDT), Fault Recovery, and Memory Partitioning (MAP) make it a strong fit for automotive body and HVAC controllers. The CWG module drives small BLDC fan motors at 25 kHz with dead-band insertion; the 5-bit DAC and op-amp-less comparator inputs handle NTC thermistor chains for cabin climate sensing. Typical architecture: PIC18F25K42-E/ML at 64 MHz coordinating CAN-LIN via UART/LIN PHY, PWM for HVAC blend door stepper, ZCD for AC zero-cross triac control. AEC-Q100 customers often select the M-class -E/ML because of its -125C top temperature and automotive PPAP support from Microchip. The Functional Safety primitives (WWDT, CRC/SCAN, Deadman Timer) help developers target ISO 26262 ASIL-aware features without external watchdog ICs.
Recommended
Industrial Sensor Signal Conditioning
The PIC18F25K42-E/ML delivers 12-bit ADC2 accuracy with hardware averaging (from 4x to 64x oversampling), ZCD for AC-line frequency detection, CLC for fault-event logic, and DMA for streaming samples into RAM buffers. The 5-bit DAC on chip sets a threshold reference, while the analog comparators provide fault-window detection for bridge sensors. Typical architecture: load-cell front end feeding ADC2 with 64x oversampling, results pushed via DMA into a 512-byte ring buffer for averaging, CLC implements a moving-average filter to reduce CPU wake events. The 2 KB SRAM holds about 250 12-bit samples plus firmware stack, with the EEPROM holding calibration constants. The -E temperature grade suits factory floor enclosures where supply chains drift above +85 C. The 28-QFN (ML) 6 x 6 mm footprint fits standard 0805 spacing on the PCB.
Recommended
Appliance and White Goods Display Controller
The PIC18F25K42-E/ML is well-suited to drive 7-segment displays, FLED keypads, and rotary encoders in white goods. The PIC18 runs PWM via Time Base 2/4/6 to multiplex displays at 200 Hz refresh with hardware auto-reload, while the CLC arranges logical event sequences. PCH hardware reads cap-touch sliders, and the 4 CLCs implement piezo-buzzer tone generation without external timers. Typical architecture: 7-segment triple-digit display multiplexed with CWG + Timer2/4/6, UART to main MCU, dedicated fault pin via CLC. The -40C to +125C rating covers oven, dishwasher, and washing-machine interior environments. Migrating from PIC18F25K22 or PIC18F25K20 is drop-in: the 28-QFN ML package and core pinout are unchanged across these K-series generations.
Recommended
Energy Harvesting / Solar Trickle-Charge Endpoint
The PIC18F25K42-E/ML's nanoWatt XLP sleep with power-down GPIO retention makes it a strong fit for energy-harvesting endpoints. Average current stays under 5 uA when ADC2 oversampling runs every 30 s, and voltage supervisor on RA0/RA1 detects battery brownout to trigger Shutdown mode. The 5-bit DAC programs a precision piezo boost tap-point while PWM drives an L-C boost. Typical architecture: solar cell -> boost converter under PWM control, MCU in Sleep most of the time, WWDT-free interrupt wake from TMR1 running off the 32 kHz INTOSC, I2C link to RF daughter module. The K42's Functional Safety CRC/SCAN ensures Flash integrity for long unattended deployments. The exposed pad on the 28-QFN ML package is bonded to VSS to act as a thermal heatsink for any short-burst 25 mA transmit events.
Recommended
Functional Safety Sensor / SIL-Aware Endpoint
The PIC18F25K42-E/ML is designed into IEC 61508 / SIL-aware firmware deployments, with Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check + Scan (CRC/SCAN) for Flash integrity, Memory Partitioning (MAP), Deadman Timer, and configuration lock bits. Engineers building sensor endpoints for industrial process control, gas detection, or fire-safety panels can use these blocks as building blocks for diagnostic routines. Typical architecture: redundant photoelectric sensor pair fed to the 12-bit ADC2 in differential mode, ADC2 threshold compare triggers firmware state machine, WWDT detects a hung CPU and forces a safe restart with GPIO latched low. The -40C to +125C operation lets the PIC18 sit in ceiling-mount fire panels or boiler rooms. Customers often pair the PIC18F25K42-E/ML with a CP-Grade certification-level downstream module, using the FuSa primitives for software-level fault detection.
Recommended
Recommended Products Summary
Engineering reference data for PIC18F25K42-E/ML — comparison, design guidance, and compliance information.
Selection Guide
Choose PIC18F25K42-I/ML instead when your application is indoor-only (industrial, consumer) and you can save about $0.10 - $0.20 per part by accepting the -40 to +85 ceiling. Both share identical silicon and PCB footprint.
Choose PIC18F24K42-E/ML if your firmware fits in 16 KB and you need the -E temperature grade; the pinout is unchanged.
Migrate to PIC18F25K40-I/ML only if you have legacy K40 firmware: expect to re-map PPS registers and accept the 10-bit ADC resolution penalty. Cross-brand alternatives are rarely drop-in for the 28-QFN ML footprint, so staying within the Microchip PIC18 K-family is the lower-risk path.
Comparison with Alternatives
| Parameter | This Product | PIC18F25K42-I/ML | PIC18F24K42-E/ML | PIC18F25K40-I/ML | PIC18F25K40T-I/ML | PIC18F25K20-E/ML |
|---|---|---|---|---|---|---|
| Package | 28-QFN (6 x 6 mm, ML) | 28-QFN (6 x 6 mm, ML) | 28-QFN (6 x 6 mm, ML) | 28-QFN (6 x 6 mm, ML) | 28-QFN (6 x 6 mm, ML) | 28-QFN (6 x 6 mm, ML) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Architecture | PIC18 8-bit RISC, 64 MHz | PIC18 8-bit RISC, 64 MHz | PIC18 8-bit RISC, 64 MHz | PIC18 8-bit RISC, 64 MHz | PIC18 8-bit RISC, 64 MHz | PIC18 8-bit RISC, 64 MHz |
| Flash / RAM / EEPROM | 32 KB / 2 KB / 256 B | 32 KB / 2 KB / 256 B | 16 KB / 2 KB / 256 B | 32 KB / 2 KB / 256 B | 32 KB / 2 KB / 256 B | 32 KB / 1.5 KB / 256 B |
| ADC Resolution | 12-bit ADC2 with Computation | 12-bit ADC2 with Computation | 12-bit ADC2 with Computation | 10-bit ADC (legacy) | 10-bit ADC (legacy) | 10-bit ADC (no Computation) |
| Temperature Range | -40C to +125C (Extended -E) | -40C to +85C (Industrial -I) | -40C to +125C (Extended -E) | -40C to +85C (Industrial -I) | -40C to +85C (Industrial -I) | -40C to +125C (Extended -E) |
| CLC / DMA | 4 CLC + DMA + WWDT (Functional Safety) | 4 CLC + DMA + WWDT | 4 CLC + DMA + WWDT | No CLC, no DMA, WWDT available | No CLC, no DMA, WWDT available | No CLC, no DMA, no WWDT |
| Datasheet Document | DS40002113A (F-family K42 datasheet) | DS40002113A | DS40002113A | DS40001702A (K40-family datasheet) | DS40001702A | DS40001361H (K20-family legacy datasheet) |
| Price @ 1k (USD, as of 2026-09-27) | $1.79 | $1.65 (I-grade typically lower than -E) | $1.60 (smaller Flash, similar grade) | $1.40 (mature K40 supply chain) | $1.40 (mature K40, TR packing code) | $1.20 (legacy K20, smallest K20 32 KB Flash) |
Key Differentiators
- Wider -40C to +125C temperature window than industrial-grade sibling (vs PIC18F25K42-I/ML)
- 12-bit ADC2 with Computation vs 10-bit legacy ADC (vs PIC18F25K40-I/ML)
- 4 Configurable Logic Cells (CLCs) and DMA engine (vs PIC18F25K20-E/ML)
- Functional Safety (FuSa) primitives for IEC 61508-aware firmware (vs PIC18F25K40-I/ML)
Design Notes
The 28-QFN (ML) package has an exposed thermal pad (EP, pin 29) that is internally bonded to VSS. Solder this pad to a PCB ground pour covering at least 50 percent of the package footprint area; without it, junction-to-ambient thermal resistance degrades from 30 C/W to over 60 C/W and the -125 C top temperature is unreachable at full 64 MHz CPU load.
Place a 1 uF X7R 0805 ceramic bypass on VDD (pin 5) within 5 mm, plus a 100 nF X7R 0402 within 1 mm of the pin. For low-power XLP Sleep currents to reach the datasheet nanowatt levels, ensure all unused I/O are configured as outputs driven low (not high-impedance inputs floating), and disable unused peripherals via the PMD register. Estimated: entering Sleep with all analog off sets Iq to about 30 nA typical (per Microchip DS40002113A table 36-2 - confirm against your revision).
Route VDD/VSS to the MCU via a star topology from a 2.5 V - 5.5 V LDO. Keep the analog AV path on a separate net with ferrite bead and 10 uF cap to VDD; the K42 has separate AVDD/AVSS pins on 28-pin parts (note: on 28-QFN ML the analog is multiplexed to VDD/VSS - confirm against datasheet). Keep the 32 kHz secondary oscillator traces short and the SOSCO/SOSCI traces guarded by a digital ground shield.
Do NOT assume K40 firmware will run unmodified on K42. The K42 PPS routing register map has new assignments and a peripheral PIE-vector table has been reorganised. Always run the Microchip PIC10/PIC12/PIC16/PIC18 Language Tool Suite (XC8 compiler 2.40+) and pull the latest Device Family Pack (DFP) for K42. Also beware that ADC2 trigger sources on K40 differ from those on K42 - code that uses Timer3-overflow trigger may need to move to Timer1 trigger on K42.
Use the PPS feature to remap peripherals to alternate pins to ease PCB layer count or escape from BGA-equivalent routing constraints. For example, route SPI1 SCK to RP5 instead of the default RC3 pin to keep the SD card interface on a single inner layer. Note: changing PPS requires unlocking the PPSLOCK register sequence - forget this and PPS writes silently fail.
Compliance Information
RoHS / REACH compliant per Microchip product page. -E temperature grade is NOT AEC-Q100 qualified as a standalone release; AEC-Q100 customer projects use the same silicon die under separate PPAP documentation. Lead-free and halogen-free per the ML package termination finish.
