PIC32MX130F128H-50I/MR - 50MHz 32-bit MCU, 128KB Flash | Microchip
MPN: PIC32MX130F128H-50I/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.2 | $4.20 |
| 10 | $3.85 | $38.50 |
| 100 | $3.42 | $342.00 |
| 500 | $3.05 | $1,525.00 |
| 1,000 | $2.75 | $2,750.00 |
PIC32MX130F128H-50I/MR Overview
A PIC32MX microcontroller is a 32-bit flash MCU family from Microchip that combines a MIPS M4K core with rich digital peripherals, suitable for connected embedded products, consumer devices, and industrial control. The PIC32MX130F128H-50I/MR is the lower-pin-count sibling in the family and targets cost-sensitive applications that still need 32-bit performance, DSP acceleration (single-cycle MAC), and ample code space. The M4K core architecture retains the PIC ecosystem's reputation for deterministic interrupt response while adding 32-bit register width and 83 DMIPS throughput at 50 MHz.
Key features highlighted in the Microchip datasheet include 128 KB single-cycle Flash, 16 KB SRAM, Peripheral Pin Select (PPS) for flexible signal routing, three I2S/SPI modules, a Parallel Master Port (PMP) with dual buffers for graphics or memory-mapped interfaces, an integrated 10-bit ADC, and CTMU for capacitive touch sensing. USB and CAN are not present on this device, so designers targeting those should look at the PIC32MX2xx/5xx siblings.
The device integrates 5 16-bit timers, 5 IC/OC/PWM channels, two I2C, two UART, and supports up to 49 digital I/O via PPS. The 64-QFN 9x9 mm package exposes most of the available peripherals and provides a thermal pad for improved heat dissipation in continuous-operation industrial environments.
Typical applications include low-cost HMI panels with small TFTs driven by PMP, consumer audio accessories using I2S, multi-protocol sensor hubs with UART and I2C bridges, capacitive touch keypads via CTMU, and small logic-replacement or protocol-bridging controllers. The wide industrial temperature range and 50 MHz headroom also suit factory sensor nodes and serial-bridge appliances.
When designing with this part, plan the PPS mapping early because PPS groups constrain which pins can be assigned to which peripherals. Always provide a 1uF + 0.1uF decoupling pair near each VDD pin and confirm that any high-frequency I/O traces are length-matched for SPI or I2S synchronous operation.
This page consolidates distributor pricing, same-family drop-in alternatives, and practical design notes not duplicated from the manufacturer datasheet, including cross-references to PIC32MX1XX/2XX/5XX 64/100-pin family siblings.
Drop-in alternatives for PIC32MX130F128H-50I/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PIC32MX130F128H-50I/MR (same form factor and footprint) — differing in ADC, Operating Temperature, Package, Core Architecture, DMA Channels.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PIC32MX170F256H-50I/MR
✅ Drop-In📋 Reference alternative (not in catalog)
PIC32MX130F064H-50I/MR
✅ Drop-In📋 Reference alternative (not in catalog)
PIC32MX150F128H-50I/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PIC32MX130F128H-I/MR
✅ Drop-In✓ In Stock
$3.05 / Unit
View Datasheet →PIC32MX130F128H-50I/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | MIPS32 M4K 32-bit RISC |
| Maximum CPU Frequency | 50 MHz |
| DMIPS Performance | 83 DMIPS |
| Program Flash | 128 KB (128K x 8) |
| SRAM | 16 KB |
| Package | 64-QFN (MR) 9x9 mm with exposed pad |
| Operating Voltage | 2.3 V to 3.6 V |
| Operating Temperature | -40 C to +85 C (Industrial) |
| I/O Pins | Up to 49 (with PPS) |
| ADC | 10-bit, up to 13 channels |
| Timers | 5 x 16-bit |
| Input Capture / Output Compare / PWM | 5 channels |
| UART | 2 |
| SPI | 3 (including I2S-capable) |
| I2C | 2 |
| PMP (Parallel Master Port) | Yes, with dual buffers |
| CTMU (Capacitive Touch) | Yes |
| Peripheral Pin Select (PPS) | Yes |
| DMA | Yes |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
PIC32MX130F128H-50I/MR Pin Configuration
| Pin 1 | RG15 — General purpose I/O with PPS |
| Pin 2 | RG12 — General purpose I/O |
| Pin 3 | RG13 — General purpose I/O |
| Pin 4 | RG14 — General purpose I/O |
| Pin 5 | VDD — Digital supply 2.3-3.6 V |
| Pin 6 | RC1 — General purpose I/O / AN |
| Pin 7 | RC2 — General purpose I/O / AN |
| Pin 8 | RC3 — General purpose I/O / AN |
| Pin 9 | RC4 — General purpose I/O / AN |
| Pin 10 | RC5 — General purpose I/O / AN |
| Pin 11 | VSS — Ground reference |
| Pin 12 | RD0 — General purpose I/O |
| Pin 13 | RD1 — General purpose I/O |
| Pin 14 | RD2 — General purpose I/O / PMD |
| Pin 15 | RD3 — General purpose I/O / PMD |
| Pin 16 | RD4 — General purpose I/O / PMD |
| Pin 17 | RD5 — General purpose I/O / PMD |
| Pin 18 | RD6 — General purpose I/O / PMD |
| Pin 19 | RD7 — General purpose I/O / PMD |
| Pin 20 | VSS — Ground reference |
| Pin 21 | RB0 — General purpose I/O / PGED |
| Pin 22 | RB1 — General purpose I/O / PGEC |
| Pin 23 | RB2 — General purpose I/O / AN |
| Pin 24 | RB3 — General purpose I/O / AN |
| Pin 25 | RB4 — General purpose I/O / AN |
| Pin 26 | RB5 — General purpose I/O / AN |
| Pin 27 | RB6 — General purpose I/O / AN |
| Pin 28 | RB7 — General purpose I/O / AN |
| Pin 29 | RB8 — General purpose I/O / AN |
| Pin 30 | RB9 — General purpose I/O / AN |
| Pin 31 | RB10 — General purpose I/O / AN |
| Pin 32 | RB11 — General purpose I/O / AN |
| Pin 33 | RB12 — General purpose I/O / AN |
| Pin 34 | RB13 — General purpose I/O / AN |
| Pin 35 | RB14 — General purpose I/O / AN |
| Pin 36 | RB15 — General purpose I/O / AN |
| Pin 37 | VSS — Ground reference |
| Pin 38 | VDD — Digital supply 2.3-3.6 V |
| Pin 39 | RF0 — General purpose I/O |
| Pin 40 | RF1 — General purpose I/O |
| Pin 41 | RF2 — General purpose I/O |
| Pin 42 | RF3 — General purpose I/O |
| Pin 43 | RF4 — General purpose I/O |
| Pin 44 | RF5 — General purpose I/O |
| Pin 45 | RF6 — General purpose I/O / IC |
| Pin 46 | RF7 — General purpose I/O / IC |
| Pin 47 | RF8 — General purpose I/O / IC |
| Pin 48 | VDD — Digital supply 2.3-3.6 V |
| Pin 49 | RG6 — General purpose I/O |
| Pin 50 | RG7 — General purpose I/O |
| Pin 51 | RG8 — General purpose I/O |
| Pin 52 | RG9 — General purpose I/O |
| Pin 53 | MCLR — Master clear reset (active low) |
| Pin 54 | RE0 — General purpose I/O / PMD |
| Pin 55 | RE1 — General purpose I/O / PMD |
| Pin 56 | RE2 — General purpose I/O / PMD |
| Pin 57 | RE3 — General purpose I/O / PMD |
| Pin 58 | RE4 — General purpose I/O / PMD |
| Pin 59 | RE5 — General purpose I/O / PMD |
| Pin 60 | RE6 — General purpose I/O / PMD |
| Pin 61 | RE7 — General purpose I/O / PMD |
| Pin 62 | AVDD — Analog supply 2.3-3.6 V |
| Pin 63 | AVSS — Analog ground |
| Pin 64 | EP — Exposed thermal pad - connect to VSS |
Typical Applications
PIC32MX130F128H-50I/MR is suitable for 6 applications: Low-Cost HMI with PMP-driven LCD, Consumer Audio Accessory with I2S Codec, Multi-Protocol Industrial Sensor Hub, Capacitive Touch Keypad with CTMU, Serial Protocol Bridge / UART-SPI-I2C Gateway, Small Logic Replacement / Glue Controller.
Low-Cost HMI with PMP-driven LCD
The PIC32MX130F128H-50I/MR suits monochrome and low-color GLCD human-machine interfaces because its Parallel Master Port exposes 8/16-bit data with separate read/write strobes and dual buffers, removing DMA strain during display refresh. The 50 MHz M4K core executes pixel-font rendering and button scanning in real time while PPS routes keypad scan lines to any spare pin. With 16 KB of SRAM, the device holds a partial framebuffer or layered text widgets without external memory, and the 64-QFN exposed pad dissipates heat in always-on industrial panels.
Recommended
Consumer Audio Accessory with I2S Codec
The PIC32MX130F128H-50I/MR's three I2S/SPI modules enable direct connection to a stereo audio codec such as an S/PDIF transmitter or a low-cost DAC, supporting sample rates up to 48 kHz from the M4K core's single-cycle MAC. Single-cycle multiply-accumulate accelerates software volume scaling and simple DSP blocks (EQ, limiting) without an external DSP. The 128 KB Flash accommodates USB HID or Bluetooth-classic control stacks paired with a UART-attached BT module, and the 64-QFN package is small enough for wearable or portable enclosures.
Recommended
Multi-Protocol Industrial Sensor Hub
The PIC32MX130F128H-50I/MR aggregates multiple sensor interfaces - 2 UART, 2 I2C, and 3 SPI - making it ideal as a protocol-bridging hub between Modbus RTU RS-485 slaves and an upstream Ethernet or CAN gateway. Its 10-bit ADC with 13 channels handles analog 4-20 mA loop inputs, while the 50 MHz core runs PID loops at update rates well above 1 kHz. The industrial -40 to +85 C rating and 64-QFN footprint allow direct PCB mounting inside IP65 enclosures without thermal concerns.
Recommended
Capacitive Touch Keypad with CTMU
The PIC32MX130F128H-50I/MR integrates Microchip's CTMU (Charge Time Measurement Unit), enabling up to 13 capacitive touch channels without an external touch controller. The M4K core runs the touch-scan scheduler and debounces while leaving cycles for backlight PWM, haptics, and USB-CDC serial output to a host. The 64-QFN 9x9 mm package mounts directly under a touch PCB or flex tail, and the industrial temperature rating supports appliance and automotive cabin controls.
Recommended
Serial Protocol Bridge / UART-SPI-I2C Gateway
As a serial gateway, the PIC32MX130F128H-50I/MR can run up to 2 UART, 2 I2C, and 3 SPI interfaces concurrently thanks to PPS, mapping any function to most digital pins. The 50 MHz core executes command parsing, checksum validation (CRC-16/32), and protocol conversion without flow-control stalls. Designers commonly use this part to bridge legacy RS-232 equipment to modern SPI sensors or to expose I2C peripherals over USB-CDC via a UART-USB bridge chip.
Recommended
Small Logic Replacement / Glue Controller
When a discrete CPLD or several 74-series logic ICs are replaced to save board area and BOM cost, the PIC32MX130F128H-50I/MR often fits the role because PPS remaps any peripheral function to any I/O pin and the M4K core executes custom glue logic with deterministic 50 MHz timing. The 128 KB Flash stores firmware-defined state machines, watchdogs, and timing patterns, while the 16 KB SRAM provides working memory for serial buffers and command queues. The 64-QFN package consolidates tens of logic functions into one IC.
Recommended
Recommended Products Summary
Engineering reference data for PIC32MX130F128H-50I/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PIC32MX170F256H-50I/MR | PIC32MX130F064H-50I/MR | PIC32MX150F128H-50I/MR | PIC32MX130F128H-I/MR |
|---|---|---|---|---|---|
| Package | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit |
| Max Frequency | 50 MHz | 50 MHz | 50 MHz | 50 MHz | 50 MHz |
| Flash | 128 KB | 256 KB | 64 KB | 128 KB | 128 KB |
| SRAM | 16 KB | 64 KB | 16 KB | 32 KB | 16 KB |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C |
| USB | No | No (170H variant) | No | No (150H variant) | No |
| PMP | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Doubling Flash headroom without PCB changes (vs PIC32MX130F064H-50I/MR)
- Higher SRAM for graphical framebuffers (vs PIC32MX130F128H-I/MR)
- Step-up path with no footprint change (vs PIC32MX130F064H-50I/MR)
Design Notes
Place a 10 uF bulk capacitor plus 0.1 uF decoupling capacitor as close as possible to each VDD/AVDD pair of the PIC32MX130F128H-50I/MR. The internal voltage regulator draws brief high-current pulses during Flash programming and peripheral activity, and inadequate decoupling causes brown-out resets that look like firmware bugs. Use short, wide traces or a dedicated power pour for VDD/VSS, and connect the QFN exposed pad (pin 64) to a continuous ground plane to provide both thermal dissipation and low-impedance return.
Route MCLR with a 10 kohm pull-up to VDD and place a 100 nF cap to ground close to the MCLR pin; this prevents spurious resets during in-circuit serial programming (ICSP) and power-up. PGEDx/PGECx lines should be as short as possible and not routed near switching signals to keep ICSP noise-free. For QFN packages, use 4-layer PCB with continuous ground plane under the device to provide thermal relief and signal reference.
Plan the Peripheral Pin Select (PPS) mapping before laying out the PCB. PPS groups restrict which peripheral functions can be assigned to which pins; remapping after design is possible in firmware but a poor initial pin assignment wastes I/O. Use the Microchip PPS configurator (part of MPLAB X) to validate the chosen pin map. For SPI and I2S, length-match clock and data lines to within 50 mil to avoid timing violations at 50 MHz peripheral clock.
Do not enable the on-chip voltage regulator's BOR (brown-out reset) at the lowest voltage unless required; many PIC32MX design issues trace to BOR triggering under momentary inrush current. Configure the device configuration bits (DEVCFG) carefully because mistakes cannot be changed in software without a programmer. The CTMU pins must be calibrated per board - stray capacitance from adjacent traces causes large touch sensitivity drift between prototypes.
Compliance Information
RoHS and lead-free per Microchip product environmental compliance. Industrial temperature -40C to +85C. Not AEC-Q100 qualified - choose PIC32MX1XX automotive variants for automotive applications.