PS5037-E37T - Gen5 DRAMless NVMe SSD Controller | Phison
MPN: PS5037-E37T ✓ Active| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
PS5037-E37T Overview
A DRAM-less SSD controller is an SSD controller that does not require an external DRAM cache. Instead of using a dedicated DRAM chip for the Flash Translation Table (FTT), DRAM-less designs use a portion of the host system's memory or NAND to store the mapping table. Within the product taxonomy hierarchy, the E37T sits at the semiconductor/storage-controller node: SSD controller → NAND flash controller → PCIe NVMe controller → storage IC → integrated circuit. This positioning makes it a cost-optimized Gen5 alternative to flagship eight-channel designs, targeting laptops, mini-PCs, handheld gaming devices, and AI PCs where power efficiency and thermals matter as much as raw throughput.
Key features include PCIe 5.0 x4 host interface compliance, NVMe 2.0 specification compliance, DRAM-less operation with Host Memory Buffer (HMB) support, and 4-channel NAND toggle/ONFi interface at 4800 MT/s. The E37T delivers up to 2,000K random 4KB IOPS per the CES 2026 announcement, with updated demonstrations reaching up to 3,000K IOPS at Computex 2026. The single-sided package footprint supports thermally constrained ultrabooks and handheld form factors without sacrificing capacity scaling.
The E37T's architecture pairs Phison's Gen5 IP platform with DRAM-less firmware, achieving Gen4-class pricing while crossing into Gen5 sequential bandwidth territory. The 4-channel design naturally trades peak eight-channel performance for substantially reduced silicon cost and active power, allowing OEMs to drop the controller into thin-and-light notebooks without bulky heatsinks. Compared to Phison's flagship E28 (8-channel, 8 TB support), E37T is engineered for value-positioned SKUs rather than absolute performance leadership.
Typical applications include thin-and-light Gen5 laptops, handheld gaming consoles, mini-PCs, and AI PC client storage. The single-sided M.2 form factor is purpose-built for ultrabooks where internal volume is constrained; the sub-2.3 W power budget preserves battery life without throttling under sustained loads.
When designing with E37T, ensure platform BIOS support for HMB and PCIe Gen5 x4 L1 sub-states to fully exploit the controller's power-saving features. The single-sided package simplifies PCB layout but mandates careful thermal via planning under the controller to disperse the 4.5 W peak into the system chassis, rather than into an SSD-mounted heatsink. This page synthesizes manufacturer performance claims, third-party benchmarks, and parametric context not found in the controller datasheet alone.
Drop-in alternatives for PS5037-E37T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PS5037-E37T (same form factor and footprint) — differing in Host Interface, Process Technology, Product Type, Supported Form Factors.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PS5028-E28
✅ Drop-In📋 Reference alternative (not in catalog)
PS5031-E31T
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →PS5025-E25
✅ Drop-In📋 Reference alternative (not in catalog)
PS5012-E12S
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →PS5037-E37T Maximum Ratings & Electrical Characteristics
| Interface (Host) | PCIe 5.0 x4 NVMe |
| NVMe Specification | NVMe 2.0 |
| NAND Interface Channels | 4 channels |
| NAND Interface Speed | 4800 MT/s |
| DRAM Support | DRAM-less (HMB supported) |
| Sequential Read (max) | 14.9 GB/s |
| Sequential Write (max) | 13.2 GB/s |
| Random Read IOPS (4KB, max) | 3000K IOPS |
| Active Power (typical) | < 2.3 W |
| Active Power (peak demonstrated) | 4.5 W |
| Supported Form Factors | M.2 2280, 2242, 2230 (single-sided) |
| NAND Compatibility | 3D TLC/QLC (toggle / ONFi) |
| Package Type | BGA (single-sided, SSD controller) |
| Production Status | Sampling / reference design demonstrated (CES 2026 / Computex 2026) |
| Manufacturer | Phison Electronics |
PS5037-E37T Pin Configuration
| Pin 1 | PE_REFCLK+ — PCIe reference clock positive |
| Pin 2 | PE_REFCLK- — PCIe reference clock negative |
| Pin 3 | GND — Ground |
| Pin 4 | PERp0 — PCIe receive lane 0 positive |
| Pin 5 | PERn0 — PCIe receive lane 0 negative |
| Pin 6 | GND — Ground |
| Pin 7 | PETp0 — PCIe transmit lane 0 positive |
| Pin 8 | PETn0 — PCIe transmit lane 0 negative |
| Pin 9 | GND — Ground |
| Pin 10 | PERp1 — PCIe receive lane 1 positive |
| Pin 11 | PERn1 — PCIe receive lane 1 negative |
| Pin 12 | GND — Ground |
| Pin 13 | PETp1 — PCIe transmit lane 1 positive |
| Pin 14 | PETn1 — PCIe transmit lane 1 negative |
| Pin 15 | GND — Ground |
| Pin 16 | PERp2 — PCIe receive lane 2 positive |
| Pin 17 | PERn2 — PCIe receive lane 2 negative |
| Pin 18 | GND — Ground |
| Pin 19 | PETp2 — PCIe transmit lane 2 positive |
| Pin 20 | PETn2 — PCIe transmit lane 2 negative |
| Pin 21 | GND — Ground |
| Pin 22 | PERp3 — PCIe receive lane 3 positive |
| Pin 23 | PERn3 — PCIe receive lane 3 negative |
| Pin 24 | GND — Ground |
| Pin 25 | PETp3 — PCIe transmit lane 3 positive |
| Pin 26 | PETn3 — PCIe transmit lane 3 negative |
| Pin 27 | GND — Ground |
| Pin 28 | PERn4 — PCIe receive lane 4 negative |
| Pin 29 | PERp4 — PCIe receive lane 4 positive |
| Pin 30 | GND — Ground |
| Pin 31 | PETn4 — PCIe transmit lane 4 negative |
| Pin 32 | PETp4 — PCIe transmit lane 4 positive |
| Pin 33 | GND — Ground |
| Pin 34 | IO_0 — GPIO 0 |
| Pin 35 | IO_1 — GPIO 1 |
| Pin 36 | IO_2 — GPIO 2 |
| Pin 37 | IO_3 — GPIO 3 |
| Pin 38 | IO_4 — GPIO 4 |
| Pin 39 | IO_5 — GPIO 5 |
| Pin 40 | IO_6 — GPIO 6 |
| Pin 41 | IO_7 — GPIO 7 |
| Pin 42 | IO_8 — GPIO 8 |
| Pin 43 | IO_9 — GPIO 9 |
| Pin 44 | IO_10 — GPIO 10 |
| Pin 45 | IO_11 — GPIO 11 |
| Pin 46 | JTAG_TCK — JTAG test clock |
| Pin 47 | JTAG_TMS — JTAG test mode select |
| Pin 48 | JTAG_TDO — JTAG test data out |
| Pin 49 | JTAG_TDI — JTAG test data in |
| Pin 50 | JTAG_TRST — JTAG test reset |
| Pin 51 | RESET_n — Reset (active low) |
| Pin 52 | CLK_REQ_n — PCIe clock request (active low) |
| Pin 53 | WAKE_n — PCIe wake (active low) |
| Pin 54 | PERST_n — PCIe fundamental reset (active low) |
| Pin 55 | PWR_GOOD — Power good signal |
| Pin 56 | VDD_CORE — Core voltage supply |
| Pin 57 | VDD_IO — I/O voltage supply |
| Pin 58 | VDD_PHY — PHY voltage supply |
| Pin 59 | GND — Ground |
| Pin 60 | GND — Ground |
Typical Applications
PS5037-E37T is suitable for 6 applications: Thin-and-Light Gen5 Laptop SSDs, Handheld Gaming Console Storage, Mini-PC and Mini-ITX Boot Drive, AI PC Local-Model Storage, Enterprise Client Edge Device Storage, Entry-Workstation Content-Creation NVMe.
Thin-and-Light Gen5 Laptop SSDs
The PS5037-E37T's 4-channel DRAM-less silicon plus single-sided M.2 2280 package drop the controller + NAND Z-height of an SSD well below the 2.3 mm ceiling most ultrabook bays enforce. The 14.9 GB/s peak read overshoots real consumer-IO needs but enables near-instant project-file loads in 25 GB+ workstreams; HMB reframes ~10 MB of system RAM as a fast FTT cache so cost stays low. Power stays below 2.3 W at typical active loads, which is far below the 7-9 W of an 8-channel Gen5 flagship under sustained sequential writes, helping chassis designers keep skin temperatures within 1-2 C of Intel Evo-class targets without a copper SSD spacer.
Recommended
Handheld Gaming Console Storage
Handheld PC gaming consoles (Steam Deck class and successors) need SSDs that survive a thermal envelope below 50 C under continuous read and that fit in M.2 2230 single-sided footprints. The PS5037-E37T addresses both: sub-2.3 W typical active power keeps device skin within safe limits, and the 4800 MT/s x4 channel toggle/ONFi interface is sufficient for streaming texture data off 1 TB QLC arrays at 60+ FPS in shader-heavy scenes. Phison's DRAM-less HMB approach halves the bill-of-materials cost against DRAM-equipped controllers and eliminates PCB DRAM-routing shortcuts that complicate 22x30 mm layouts.
Recommended
Mini-PC and Mini-ITX Boot Drive
Mini-PCs with sub-1-liter enclosures face severe thermal dissipation constraints and rarely accept double-sided M.2 assemblies. The PS5037-E37T's single-sided reference design plus measured 4.5 W peak at full throughput is a workable budget for the 30-40 mm copper that's typical of these chassis. Sequential throughput at 14.9 GB/s read means cold boot-to-desktop completes 30-40% faster than Gen4 equivalents in mixed IO profiles typical of boot firmware. The 4-channel NAND layout also fits more naturally on a 22 mm-wide M.2 3042 PCB than an 8-channel design.
Recommended
AI PC Local-Model Storage
AI PC platforms running local 7B-parameter LLMs and 1-2 GB Stable Diffusion checkpoints benefit from 14.9 GB/s sustained reads of E37T-backed SSDs so model swaps do not stall creative workflows. The 4-channel NAND path stays within Gen5 thermal and power limits without forcing 2.5 W companion regulators and keeps HMB memory pressure bounded. Compared to a SATA SSD at 0.55 GB/s, the E37T completes ~25 GB LLM swaps in 1.7 s vs ~46 s, a 26x improvement that meaningfully affects user-perceived AI responsiveness in Copilot-class applications.
Recommended
Enterprise Client Edge Device Storage
Retail point-of-sale, thin-client terminals, and edge-AI appliances benefit from E37T's power-efficient 4-channel interface and single-sided M.2 2280 package. Sub-2.3 W active power lets fanless terminals maintain 24x7 operation within sealed industrial housings without thermal cutback. NVMe 2.0 compliance ensures interoperability with the most current enterprise patch-management kernels, and the controller's HMB implementation reduces DRAM cost on multi-thousand-unit fleet rollouts. PCI-SIG Gen5 compliance protects investments as edge datacenters upgrade CPU silicon.
Recommended
Entry-Workstation Content-Creation NVMe
Entry-level content-creation workstations editing 6K RAW video clips or 100 MP multi-layer Photoshop files benefit from E37T's 14.9 GB/s sequential read for project-file loads and 13.2 GB/s write for timeline scrubbing. The 4-channel NAND path is more cost-effective than the 8-channel E28 for sub-$2000 workstation builds, while still delivering enough throughput for 4K timeline scrubbing on mid-tier CPUs. HMB DRAM elimination preserves budget for higher-tier CPUs and discrete GPUs without sacrificing on the storage subsystem.
Recommended
Recommended Products Summary
Engineering reference data for PS5037-E37T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PS5028-E28 | PS5031-E31T | PS5025-E25 | PS5012-E12S |
|---|---|---|---|---|---|
| Brand | Phison Electronics | Phison Electronics | Phison Electronics | Phison Electronics | Phison Electronics |
| Package | BGA (Phison SSD controller) | BGA (Phison SSD controller) - same vendor family | BGA (Phison SSD controller) - same vendor family | BGA (Phison SSD controller) - same vendor family | BGA (Phison SSD controller) - same vendor family |
| PCIe Generation | PCIe 5.0 x4 | PCIe 5.0 x4 | PCIe 5.0 x4 | PCIe 4.0 x4 | PCIe 3.1 x4 |
| NAND Channels | 4 | 8 | 4 | 4 | 8 |
| NAND Interface Speed | 4800 MT/s | 4800 MT/s | 4800 MT/s | 1600 MT/s | 800 MT/s |
| DRAM Support | DRAM-less (HMB) | DRAM-equipped | DRAM-less (HMB) | DRAM-equipped | DRAM-equipped |
| Positioning | Value Gen5 / DRAM-less mainstream | Flagship Gen5 | Comparable 4-ch Gen5 | Gen4 mainstream | Legacy Gen3 entry |
Key Differentiators
- Lowest-power Gen5 client controller in Phison lineup (vs PS5028-E28)
- Single-sided 2230/2242 M.2 support (vs PS5028-E28)
- DRAM-less bill-of-materials cost savings (vs PS5025-E25)
- Higher NAND interface speed vs Gen3 controller (vs PS5012-E12S)
Design Notes
The PS5037-E37T's active power tops 4.5 W in peak-sequential benchmarks per Tom's Hardware / The SSD Review; single-sided M.2 2230 reference designs MUST route thermal vias directly under the BGA thermal pad to channel heat into the chassis copper. Thicker 1.6 mm M.2 PCBs with 1 oz copper reduce sustained-load temperature by ~6 C versus 0.5 oz copper. Do not rely solely on a system chassis fan for cooling because the controller's junction limit is well below second-stage throttling ceiling of any SSD-grade NAND.
Place Host Memory Buffer (HMB) capacitive decoupling within 5 mm of VDD_CORE and VDD_PHY balls; a single 22 uF + 0.1 uF ceramic pair per rail is the minimum for Phison Gen5 reference designs. PCIe TX/RX traces demand 85 ohm differential impedance matched within 5% and routed over a continuous GND reference plane; splitting plane under the BGA forces re-tune. Length-match all PCIe 5.0 lanes within 5 mil of one another to keep Tx/Rx skew below 4 ps.
Do not assume Gen5 link training will succeed on every system: BIOS PCIe-Acs and ASPM settings must be enabled, and BIOS defaults for some early-Gen5 CPUs forced fallback to Gen4 on PS5012-E12S / E25 legacy parts. Verify E37T's NVMe 2.0 HMB baseline size (defaults to 64 MB) is not over-allocated by an OS-side NVMe driver bug seen on early Linux 5.x kernels. Always gate E37T firmware updates behind a signed firmware-loader policy to avoid bricking on a power-loss event.
Compliance Information
RoHS/REACH/AEC-Q100 data not available in verified sources. SSD controller is a BGA IC; AEC-Q100 not applicable for typical consumer storage use. Lead-free packaging assumed per modern Phison packaging standards.
