R7F7010133AFP#KA4 - RH850/F1L 32-Bit 80MHz MCU 512KB Flash | Renesas
MPN: R7F7010133AFP#KA4 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.45 | $745.00 |
| 500 | $6.2 | $3,100.00 |
| 1,000 | $5.4 | $5,400.00 |
R7F7010133AFP#KA4 Overview
What is an RH850 microcontroller? The RH850 is Renesas' 32-bit automotive RISC architecture designed around a multi-core, lockstep-capable pipeline with tightly coupled ECC-protected SRAM and hardware safety hooks (ECC, MBIST, voltage/clock monitors). It sits in the broader automotive MCU hierarchy as: automotive MCU -> 32-bit MCU -> RH850 family -> RH850/F1L sub-family. The RH850/F1L variant trades higher pin counts and larger Flash for cost-sensitive body and chassis applications.
Key features include 512 KB of code Flash, 80 MHz maximum operating frequency, integrated CAN/LIN/UART communication peripherals typical of the F1L series, on-chip debugger support, and AEC-Q100 qualification. The 64-LFQFP (10x10) package offers a 0.5 mm pitch footprint suitable for reflow-compatible automotive PCB assembly.
The R7F7010133AFP#KA4 uses the RH850G3K 32-bit RISC core with single-precision FPU support and a tightly coupled instruction/data memory hierarchy. Built on a low-power automotive process, the device integrates multiple analog and digital peripherals including 12-bit ADC, timers, and communication channels directly on-die, reducing external component count and BOM cost in body control modules.
Typical applications include automotive body control modules (BCM), door/window/seat controllers, HVAC climate control, instrument cluster sub-MCUs, lighting ECUs, and small sensor-hub nodes in zonal architectures. The RH850/F1L is commonly co-deployed with a higher-pin-count F1K/F1M device for communication gateway or domain controller roles.
When designing with this part, plan for an RH850-specific toolchain (Green Hills MULTI, IAR EW for RH850, or Renesas CS+) and the E1/E20/E2 emulator for debug. Verify pinout against the specific F1L datasheet revision because the F1L family has multiple Flash/RAM variants sharing the same 64-LFQFP outline.
This page synthesizes verified distributor stock, parametric compatibility data, and practical design considerations for engineers evaluating the R7F7010133AFP#KA4 as a drop-in part or a fresh design selection.
Drop-in alternatives for R7F7010133AFP#KA4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
R7F7010133AFP-C#KA4
✅ Drop-In📋 Reference alternative (not in catalog)
R7F7010133AFP-C#AA4
✅ Drop-In📋 Reference alternative (not in catalog)
R7F7010293AFP#AA4
✅ Drop-In📋 Reference alternative (not in catalog)
R7F7010133AFP#AA4
✅ Drop-In📋 Reference alternative (not in catalog)
R7F7010113AFP#KA4
✅ Drop-In📋 Reference alternative (not in catalog)
R7F7010133AFP#KA4 Maximum Ratings & Electrical Characteristics
| Product Series | RH850/F1L |
| Core Architecture | RH850G3K (32-bit RISC) |
| CPU Bit Width | 32-bit |
| Maximum Clock Frequency | 80 MHz |
| Program Memory Size | 512 KB (512K x 8) Flash |
| Package | 64-LFQFP (10x10 mm) |
| Mounting Type | Surface Mount |
| Pin Count | 64 pins |
| Lead Pitch | 0.5 mm |
| Communication Interfaces | CAN, LIN, UART (per F1L family) |
| AEC-Q100 Qualification | Qualified (automotive grade per F1L family) |
| On-chip Debug | Yes (RH850 debug interface) |
| RoHS Status | Compliant (per distributor listings) |
R7F7010133AFP#KA4 Pin Configuration
| Pin 1 | VCC — Core supply voltage |
| Pin 2 | VSS — Ground |
| Pin 3 | RESET — Reset input (active low) |
| Pin 4 | MD0 — Mode pin 0 |
| Pin 5 | MD1 — Mode pin 1 |
| Pin 6 | TOOL0 — On-chip debug data |
| Pin 7 | TOOL1 — On-chip debug clock |
| Pin 8 | P0_0 — GPIO port 0 bit 0 / peripheral |
| Pin 9 | P0_1 — GPIO port 0 bit 1 / peripheral |
| Pin 10 | P0_2 — GPIO port 0 bit 2 / peripheral |
| Pin 11 | P0_3 — GPIO port 0 bit 3 / peripheral |
| Pin 12 | P1_0 — GPIO port 1 bit 0 |
| Pin 13 | P1_1 — GPIO port 1 bit 1 |
| Pin 14 | P1_2 — GPIO port 1 bit 2 |
| Pin 15 | P1_3 — GPIO port 1 bit 3 |
| Pin 16 | VCC — I/O supply voltage |
| Pin 17 | VSS — Ground |
| Pin 18 | P2_0 — GPIO port 2 bit 0 |
| Pin 19 | P2_1 — GPIO port 2 bit 1 |
| Pin 20 | P2_2 — GPIO port 2 bit 2 |
| Pin 21 | P2_3 — GPIO port 2 bit 3 |
| Pin 22 | P3_0 — GPIO port 3 bit 0 |
| Pin 23 | P3_1 — GPIO port 3 bit 1 |
| Pin 24 | P3_2 — GPIO port 3 bit 2 |
| Pin 25 | P3_3 — GPIO port 3 bit 3 |
| Pin 26 | P4_0 — GPIO port 4 bit 0 / CAN0 TX |
| Pin 27 | P4_1 — GPIO port 4 bit 1 / CAN0 RX |
| Pin 28 | P4_2 — GPIO port 4 bit 2 / LIN0 TX |
| Pin 29 | P4_3 — GPIO port 4 bit 3 / LIN0 RX |
| Pin 30 | VSS — Ground |
| Pin 31 | VCC — Core supply voltage |
| Pin 32 | P5_0 — GPIO port 5 bit 0 / UART0 TX |
| Pin 33 | P5_1 — GPIO port 5 bit 1 / UART0 RX |
| Pin 34 | P5_2 — GPIO port 5 bit 2 |
| Pin 35 | P5_3 — GPIO port 5 bit 3 |
| Pin 36 | P6_0 — GPIO port 6 bit 0 / timer output |
| Pin 37 | P6_1 — GPIO port 6 bit 1 / timer output |
| Pin 38 | P6_2 — GPIO port 6 bit 2 / timer output |
| Pin 39 | P6_3 — GPIO port 6 bit 3 / timer output |
| Pin 40 | VSS — Ground |
| Pin 41 | AVCC — Analog supply voltage |
| Pin 42 | AVSS — Analog ground |
| Pin 43 | AN0 — ADC analog input 0 |
| Pin 44 | AN1 — ADC analog input 1 |
| Pin 45 | AN2 — ADC analog input 2 |
| Pin 46 | AN3 — ADC analog input 3 |
| Pin 47 | AN4 — ADC analog input 4 |
| Pin 48 | AN5 — ADC analog input 5 |
| Pin 49 | AN6 — ADC analog input 6 |
| Pin 50 | AN7 — ADC analog input 7 |
| Pin 51 | P8_0 — GPIO port 8 bit 0 |
| Pin 52 | P8_1 — GPIO port 8 bit 1 |
| Pin 53 | P8_2 — GPIO port 8 bit 2 |
| Pin 54 | P8_3 — GPIO port 8 bit 3 |
| Pin 55 | VSS — Ground |
| Pin 56 | VCC — I/O supply voltage |
| Pin 57 | P9_0 — GPIO port 9 bit 0 |
| Pin 58 | P9_1 — GPIO port 9 bit 1 |
| Pin 59 | P9_2 — GPIO port 9 bit 2 |
| Pin 60 | P9_3 — GPIO port 9 bit 3 |
| Pin 61 | P10_0 — GPIO port 10 bit 0 |
| Pin 62 | P10_1 — GPIO port 10 bit 1 |
| Pin 63 | P10_2 — GPIO port 10 bit 2 / interrupt |
| Pin 64 | P10_3 — GPIO port 10 bit 3 / interrupt |
Typical Applications
R7F7010133AFP#KA4 is suitable for 6 applications: Automotive Body Control Module (BCM), Door Module / Seat Controller, HVAC Climate Control ECU, Automotive Lighting ECU, Sensor Hub / Zonal Node MCU, Instrument Cluster Sub-MCU.
Automotive Body Control Module (BCM)
The R7F7010133AFP#KA4 is well suited for body control modules because its 512 KB Flash at 80 MHz easily runs CAN/LIN stacks plus BCM state machines for central locking, wiper control, and turn-signal sequencing. The 64-LFQFP outline keeps the PCB compact for under-dash mounting, while AEC-Q100 qualification ensures compliance with passenger cabin thermal and EMC requirements.
Recommended
Door Module / Seat Controller
Door modules and seat controllers need ASIL-graded compute to drive window lift, mirror fold, and seat position motors. The R7F7010133AFP#KA4's RH850G3K core delivers deterministic interrupt latency for LIN-connected door nodes, while on-chip 12-bit ADC and PWM timers handle current sensing for stall detection. The 64-LFQFP gives enough I/O for 4 window channels plus mirror/seat switch matrix without an external I/O expander.
Recommended
HVAC Climate Control ECU
HVAC ECUs need reliable 32-bit performance for closed-loop temperature and blower control. R7F7010133AFP#KA4's 80 MHz RH850 core plus on-chip ADC/PWM suit PID loops driving mixed-water valves and BLDC blower motors, while CAN-FD connectivity integrates with the vehicle network. AEC-Q100 grade 1 (-40C..-125C) operation is standard for F1L-family parts in HVAC mounting locations under the dash.
Recommended
Automotive Lighting ECU
LED headlamp and tail-light ECUs require precise PWM to drive constant-current LED strings and matrix-beam patterns. The R7F7010133AFP#KA4's timer peripherals and DMA support flicker-free PWM at frequencies above 200 Hz, while CAN/LIN connectivity allows OTA-friendly lighting feature updates. The 64-LFQFP leaves headroom for LIN daisy-chaining of lamp nodes with a master BCM.
Recommended
Sensor Hub / Zonal Node MCU
In zonal E/E architectures, small ECUs aggregate radar, ultrasonic, and IMU sensors. R7F7010133AFP#KA4 acts as a sensor hub MCU because its 80 MHz core plus FPU can run basic sensor fusion, while its AEC-Q100 rating handles under-bumper or behind-bumper thermal stress. The 512 KB Flash supports CAN-FD offload of processed sensor data toward the central vehicle computer.
Recommended
Instrument Cluster Sub-MCU
Instrument clusters often split duties between a graphics-rich main MCU and a smaller sub-MCU for indicator lamps, gauge stepper motors, and telltale diagnostics. The R7F7010133AFP#KA4 in 64-LFQFP is a cost-effective sub-MCU that drives stepper motors via its timers while CAN-FD talks to the main cluster SoC. AEC-Q100 and -40C..-125C operation match cluster cabin thermal requirements.
Recommended
Recommended Products Summary
Engineering reference data for R7F7010133AFP#KA4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | R7F7010133AFP-C#KA4 | R7F7010133AFP-C#AA4 | R7F7010293AFP#AA4 | R7F7010133AFP#AA4 | R7F7010113AFP#KA4 |
|---|---|---|---|---|---|---|
| Package | 64-LFQFP (10x10 mm) | 64-LFQFP (10x10 mm) - same | 64-LFQFP (10x10 mm) - same | 64-LFQFP (10x10 mm) - same | 64-LFQFP (10x10 mm) - same | 64-LFQFP (10x10 mm) - same |
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Core | RH850G3K 32-bit | RH850G3K 32-bit | RH850G3K 32-bit | RH850G3K 32-bit | RH850G3K 32-bit | RH850G3K 32-bit |
| Max Clock | 80 MHz | 80 MHz | 80 MHz | 80 MHz | 80 MHz | 80 MHz |
| Series | RH850/F1L | RH850/F1L | RH850/F1L | RH850/F1L | RH850/F1L | RH850/F1L |
| AEC-Q100 | Qualified | Qualified | Qualified | Qualified | Qualified | Qualified |
| Toolchain | GHS MULTI / IAR / CS+ | GHS MULTI / IAR / CS+ | GHS MULTI / IAR / CS+ | GHS MULTI / IAR / CS+ | GHS MULTI / IAR / CS+ | GHS MULTI / IAR / CS+ |
Key Differentiators
- Same-footprint drop-in with multiple suffix variants for supply flexibility (vs R7F7010133AFP-C#KA4)
- Higher Flash tier within F1L family footprint (vs R7F7010293AFP#AA4)
- Cost-optimized lower Flash density at same 80 MHz (vs R7F7010113AFP#KA4)
Design Notes
Route the 64-LFQFP (10x10, 0.5 mm pitch) with 4-layer stack-up: top signal, inner ground, inner power, bottom signal. Place decoupling 100 nF + 4.7 uF X7R ceramics within 2 mm of each VCC/VSS pair. Add a 10 uF bulk tantalum near AVCC. Keep ADC traces (AN0-AN7) length-matched and routed away from CAN/LIN switching nodes to avoid coupling.
RH850/F1L parts require Renesas-specific boot-mode pin strapping on MD0/MD1 - misconfiguring these locks the MCU in single-chip mode or serial-programming mode at reset. Always assert RESET with the MD pins held stable for at least 4 clock cycles. Verify the toolchain's F1L linker script matches the 512 KB Flash layout; using the wrong script silently overwrites the option-byte region.
AEC-Q100 grade 1 (-40C..-125C junction) is required for under-hood modules. At 80 MHz with all peripherals active, typical core dissipation stays under 200 mW - no heatsink required for the 64-LFQFP. Estimated: at ambient 85C inside a sealed BCM, junction rise is ~15C above ambient, leaving 25C margin to the 125C limit. Do not reduce copper area below 4 thermal vias on the exposed pad row.
Compliance Information
AEC-Q100 automotive grade per RH850/F1L family. RoHS and REACH compliance per Renesas product page.
