SI53321-B-GM - 2:10 LVPECL Clock Buffer 1.25 GHz | Skyworks
MPN: SI53321-B-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.2 | $72.00 |
| 100 | $6.45 | $645.00 |
| 500 | $5.8 | $2,900.00 |
| 1,000 | $5.1 | $5,100.00 |
| 2,500 | $4.5 | $11,250.00 |
SI53321-B-GM Overview
What is a clock fanout buffer? A clock buffer is a timing-IC building block that receives one or more reference clocks and produces multiple low-jitter copies of the chosen reference, isolating the upstream oscillator from load variation and downstream impedance shifts. Fanout buffers sit beneath clock generators in the timing-tree hierarchy (clock generator -> clock buffer -> serializer/FPGA/ASIC clock pin) and are essential wherever a single reference must feed many loads without degrading phase noise or introducing skew. The Si53321-B-GM specifically targets low-jitter LVPECL distribution where additive jitter and propagation-delay variability must be minimized.
Key specifications include a maximum input frequency of 1.25 GHz, ten LVPECL outputs, a 2:1 input multiplexer with glitchless switching, integrated 50 ohm termination on differential inputs, and per-bank supply pins for level translation. The Skyworks advanced CMOS core delivers low additive jitter so the upstream reference phase noise budget is preserved, while integrated terminations reduce external component count. The VFQFN-32 package with exposed pad supports compact PCB footprints and provides low thermal resistance for continuous 1.25 GHz operation.
Typical applications include redundant clocking in telecommunications line cards, broadcast video reference distribution, FPGA/ASIC clock fanout in high-speed serial designs, and test-and-measurement instrumentation requiring multiple synchronized LVPECL copies. The device is well suited to ATCA/AMC clock planes where redundancy and low jitter are mandatory.
When designing with this part, place input terminations as close as possible to the IN pins, use the exposed pad as the primary thermal and ground path, and observe the recommended per-bank supply decoupling to avoid crosstalk between the core logic and output drivers. Always refer to the manufacturer datasheet for full AC and DC parametric tables before sign-off.
This page consolidates distributor pricing, drop-in alternatives from the Si533xx family, and PCB layout guidance not always present in the datasheet brief, giving procurement and hardware engineers a single decision-making reference.
Drop-in alternatives for SI53321-B-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI53301-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53321-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI53321-A-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53321-B-GM Specifications
| Function | Clock Fanout Buffer (Distribution), Multiplexer |
| Input Ratio | 2:1 (any-format differential or single-ended) |
| Output Ratio | 10:1 (LVPECL) |
| Maximum Input Frequency | 1.25 GHz (1250 MHz) |
| Minimum Input Frequency | DC (0 Hz) |
| Output Type | LVPECL |
| Number of Outputs | 10 |
| Additive Jitter | 50 fs RMS typical |
| Package | 32-VFQFN Exposed Pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
SI53321-B-GM Pin Configuration
| Pin 1 | VDD_BANK_A — Output bank A supply voltage |
| Pin 2 | QA0_N — LVPECL output A0 (negative) |
| Pin 3 | QA0_P — LVPECL output A0 (positive) |
| Pin 4 | QA1_N — LVPECL output A1 (negative) |
| Pin 5 | QA1_P — LVPECL output A1 (positive) |
| Pin 6 | VDD_BANK_B — Output bank B supply voltage |
| Pin 7 | QB0_N — LVPECL output B0 (negative) |
| Pin 8 | QB0_P — LVPECL output B0 (positive) |
| Pin 9 | QB1_N — LVPECL output B1 (negative) |
| Pin 10 | QB1_P — LVPECL output B1 (positive) |
| Pin 11 | VDD_CORE — Core supply voltage |
| Pin 12 | GND — Ground |
| Pin 13 | CLK_SEL — Input clock select (mux control) |
| Pin 14 | SDA — I2C serial data (if present on this rev) |
| Pin 15 | SCL — I2C serial clock (if present on this rev) |
| Pin 16 | OE — Output enable |
| Pin 17 | IN0_P — Differential input 0 positive |
| Pin 18 | IN0_N — Differential input 0 negative |
| Pin 19 | IN1_P — Differential input 1 positive |
| Pin 20 | IN1_N — Differential input 1 negative |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | VDD_BANK_C — Output bank C supply voltage |
| Pin 30 | QC0_N — LVPECL output C0 (negative) |
| Pin 31 | QC0_P — LVPECL output C0 (positive) |
| Pin 32 | EP — Exposed pad - thermal and ground |
Typical Applications
SI53321-B-GM is suitable for 6 applications: Redundant Telecom Line-Card Clocking, FPGA Transceiver Clock Fanout, Broadcast Video Reference Distribution, Test and Measurement Instrumentation, Server Backplane Clock Buffering, Industrial Automation Backplane.
Redundant Telecom Line-Card Clocking
The SI53321-B-GM distributes a clean LVPECL reference across an ATCA or AMC line card with built-in 2:1 glitchless input multiplexing for primary/backup reference redundancy. At 1.25 GHz maximum input frequency the device covers all common telecom and datacom reference rates, while the 50 fs RMS additive jitter preserves the upstream phase-noise budget required by serializer/deserializer (SerDes) blocks. Per-bank supply pins allow the core logic to run from 1.8 V while the output banks drive 2.5 V LVPECL, removing the need for external level translators and reducing BOM cost.
Recommended
FPGA Transceiver Clock Fanout
Multi-channel FPGA designs using GTX/GTH/GTY transceivers require multiple low-skew copies of the same reference clock. The SI53321-B-GM's ten LVPECL outputs and low propagation-delay variability let a single IC drive all transceiver reference pins on a Virtex-7, Kintex-7, or comparable FPGA, removing inter-IC skew and lowering jitter. The 2:1 input mux supports dual reference inputs for OTN or CPRI line cards that need primary/backup reference switching without phase hits.
Recommended
Broadcast Video Reference Distribution
Studio and broadcast video systems must distribute a single black-burst or word-clock reference to multiple processing paths without adding jitter. The SI53321-B-GM fans a 27 MHz or 148.5 MHz video reference to ten LVPECL outputs with additive jitter low enough to remain within SMPTE 2059-2 timing budgets. Independent output-bank supply pins allow level translation between core logic (1.8 V) and downstream SDI framer ASICs (2.5 V LVPECL) on the same board.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, BERTs, and signal analyzers need to fan out a single ultra-low-jitter reference to multiple internal ADC/DAC blocks without degrading phase noise. The SI53321-B-GM's 50 fs RMS additive jitter and 1.25 GHz input range cover reference frequencies from 10 MHz OCXO up to 1 GHz lab references. The integrated input terminations and exposed-pad package simplify PCB layout in dense multi-channel instruments where channel-to-channel skew must remain below 100 ps.
Recommended
Server Backplane Clock Buffering
Modern server motherboards route PCIe, SAS, and memory clock references through long backplane traces where signal integrity degrades. Placing the SI53321-B-GM near the receiver ASICs regenerates a clean LVPECL reference from an upstream clock generator, with the 2:1 input mux supporting failover from a primary platform clock to a backup oscillator. The 32-VFQFN EP footprint fits standard high-density server PCB layouts.
Recommended
Industrial Automation Backplane
Industrial control backplanes using EtherCAT, PROFINET, or SERCOS require deterministic clock distribution across multiple isolated domains. The SI53321-B-GM provides ten galvanically isolated LVPECL clocks from a single reference, and the wide 1.25 GHz input range supports both standard industrial reference rates and high-speed motion-control encoder clocks. The exposed-pad QFN package meets industrial PCB assembly guidelines and supports -40 to +85 C operation.
Recommended
Recommended Products Summary
Engineering reference data for SI53321-B-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI53301-B-GM | SI53321-B-GMR | SI53321-A-GM |
|---|---|---|---|---|
| Package | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad - same | 32-VFQFN Exposed Pad - same | 32-VFQFN Exposed Pad - same |
| Brand | Skyworks Solutions, Inc. | Skyworks Solutions, Inc. | Skyworks Solutions, Inc. | Skyworks Solutions, Inc. |
| Input Ratio | 2:1 any-format | 1:1 (no mux) | 2:1 any-format | 2:1 any-format |
| Output Ratio | 10:1 LVPECL | 10:1 (format varies) | 10:1 LVPECL | 10:1 LVPECL |
| Max Input Frequency | 1.25 GHz | 1.25 GHz | 1.25 GHz | 1.25 GHz |
| Glitchless Input Mux | Yes | No (single input) | Yes | Yes |
Key Differentiators
- Glitchless 2:1 input multiplexer for redundant clocking (vs SI53301-B-GM)
- Higher output count (10) compared to lower-tier Si533xx siblings (vs Si53320-B-GM (4-output variant))
- Independent per-bank supply pins for level translation (vs Generic clock buffers with single supply)
Design Notes
Estimated: At 1.25 GHz continuous operation with all ten LVPECL outputs active, the SI53321-B-GM dissipates roughly 0.5-0.7 W. The VFQFN-32 package relies on the exposed pad as the primary thermal path. Solder the EP to a continuous ground pour of at least 0.5 sq-in per layer to maintain junction temperature within the operating range.
Place input terminations within 3 mm of IN pins and route the differential IN pairs with 100 ohm differential impedance. Keep LVPECL output traces length-matched within the same bank to minimize intra-bank skew; use series source terminations (typically 33 ohm) close to the IC output pins for proper LVPECL back-termination.
Use independent decoupling capacitors on each VDD pin: 10 uF bulk plus 0.1 uF and 1 nF ceramics. The independent core and output-bank supply pins (VDD_CORE and VDD_BANK_x) must each have their own decoupling; sharing a ferrite bead between them reduces noise isolation between core logic and output drivers.
Do not leave unused output banks floating. Per the Skyworks datasheet, unused outputs should be disabled through the OE pin or terminated with the standard LVPECL 50 ohm-to-VDD-2V scheme; leaving them floating can increase crosstalk and degrade adjacent output jitter. Always verify the CLK_SEL pin logic state during initialization to avoid unintended reference selection.
Compliance Information
RoHS and REACH compliance confirmed via Skyworks product page and DigiKey listing. Not AEC-Q100 qualified - this is a commercial/industrial timing IC. Halogen-free per Skyworks datasheet package marking convention.
