SI5332A-D-GM1 - 6-Output Any-Frequency Clock Generator, 333.33 MHz | Skyworks
MPN: SI5332A-D-GM1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.84 | $8.84 |
| 10 | $7.95 | $79.50 |
| 100 | $6.71 | $671.00 |
| 500 | $5.89 | $2,945.00 |
| 1,000 | $5.21 | $5,210.00 |
SI5332A-D-GM1 Overview
A clock generator IC is a semiconductor device that produces one or more precise timing reference signals from a single input reference, typically replacing multiple crystal oscillators and reducing board space. Clock generators sit within the broader timing-and-clock hierarchy of clock IC -> clock generator -> frequency synthesizer -> timing IC -> power-management IC, and they are essential building blocks in any system where multiple digital subsystems require synchronized reference clocks such as processors, FPGAs, ASICs, PHYs, transceivers, and ADCs/DACs.
Key features of the SI5332A-D-GM1 include an output frequency range of 5 MHz to 333.33 MHz, six independently configurable outputs, integer and fractional MultiSynth dividers per output, hardware control pins for output enable and frequency control, configurable signal formats (LVDS, LVPECL, HCSL, CMOS), and an I2C/SPI programmable interface. The device operates from a single 2.5 V or 3.3 V supply and supports an external crystal or differential clock as the reference.
The MultiSynth fractional divider architecture allows non-integer frequency synthesis while maintaining low phase noise and jitter, eliminating the need for separate crystal-oscillator SKUs per output frequency. The integrated PLL, combined with the configurable output drivers, lets a single device replace up to six discrete oscillators in mixed-supply designs.
Typical applications for the SI5332A-D-GM1 include 10/25/40/100G Ethernet switch and router clock trees, FPGA/ASIC reference-clock generation in industrial and communications systems, multi-channel ADC/DAC sampling-clock generation, test-and-measurement instrumentation, and PCI Express Gen 2/3/4 reference-clock generation. When designing with this device, follow the Skyworks Si5332 Reference Manual PCB-layout recommendations for the external crystal or differential reference, and keep input traces short to achieve the specified 190 fs RMS jitter performance. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for SI5332A-D-GM1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5332A-D-GM1 (same form factor and footprint) — differing in Divider Architecture, Function, Operating Temperature Range, Package, Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5332A-D-AM1
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332B-D-GM1
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332C-D-GM1
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332D-D-GM1
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332G-D-GM1
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332A-D-AM2
✅ Drop-In📋 Reference alternative (not in catalog)
SI5332A-D-GM1 Specifications
| Function | Clock Generator, Any-Frequency (INT+FRAC) |
| Number of Outputs | 6 |
| Output Frequency Range | 5 MHz to 333.33 MHz |
| Output Jitter | 190 fs RMS (typ) |
| Input Reference | External crystal (XA/XB) or differential clock |
| Divider Architecture | MultiSynth fractional and integer dividers |
| Output Format | LVDS / LVPECL / HCSL / CMOS (configurable per output) |
| Supply Voltage | 2.5 V or 3.3 V (single supply) |
| Programmable Interface | I2C / SPI |
| Hardware Control Pins | Up to 5 user-defined (OE, freq select, spread spectrum, ref select) |
| Package | 32-VFQFN Exposed Pad |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40C to +85C (industrial) |
| RoHS Status | Compliant |
SI5332A-D-GM1 Pin Configuration
| Pin 1 | VDD — Core supply (2.5 V or 3.3 V) |
| Pin 2 | VDD_DIG — Digital supply |
| Pin 3 | VDD_XTAL — Crystal oscillator supply |
| Pin 4 | XA — Crystal reference input A |
| Pin 5 | XB — Crystal reference input B |
| Pin 6 | GND_XTAL — Crystal oscillator ground |
| Pin 7 | CLKIN — Differential clock input + |
| Pin 8 | CLKIN_N — Differential clock input - |
| Pin 9 | VDDO0 — Output bank 0 supply |
| Pin 10 | OUT0 — Clock output 0 |
| Pin 11 | OUT0_N — Complementary clock output 0 |
| Pin 12 | VDDO1 — Output bank 1 supply |
| Pin 13 | OUT1 — Clock output 1 |
| Pin 14 | OUT1_N — Complementary clock output 1 |
| Pin 15 | VDDO2 — Output bank 2 supply |
| Pin 16 | OUT2 — Clock output 2 |
| Pin 17 | OUT2_N — Complementary clock output 2 |
| Pin 18 | VDDO3 — Output bank 3 supply |
| Pin 19 | OUT3 — Clock output 3 |
| Pin 20 | OUT3_N — Complementary clock output 3 |
| Pin 21 | VDDO4 — Output bank 4 supply |
| Pin 22 | OUT4 — Clock output 4 |
| Pin 23 | OUT4_N — Complementary clock output 4 |
| Pin 24 | VDDO5 — Output bank 5 supply |
| Pin 25 | OUT5 — Clock output 5 |
| Pin 26 | OUT5_N — Complementary clock output 5 |
| Pin 27 | SCL/SPI_SCK — I2C clock / SPI clock |
| Pin 28 | SDA/SPI_MOSI — I2C data / SPI data input |
| Pin 29 | A0/SPI_CS — I2C address bit / SPI chip select |
| Pin 30 | OE_FSEL0 — Hardware pin: Output enable / frequency select 0 |
| Pin 31 | FSEL1_SS_EN — Hardware pin: Frequency select 1 / spread-spectrum enable |
| Pin 32 | RESET — Reset (active low) |
| Pin EP | ePAD — Thermal pad (must be soldered to GND) |
Typical Applications
SI5332A-D-GM1 is suitable for 6 applications: 10/25/40/100G Ethernet Switch Clock Tree, FPGA / ASIC Reference Clock Generation, Multi-Channel ADC / DAC Sampling Clock Generation, Test & Measurement Instrumentation, PCI Express Reference Clock Generation, Industrial Mixed-Voltage Clock Distribution.
10/25/40/100G Ethernet Switch Clock Tree
The SI5332A-D-GM1 is purpose-built for 10/25/40/100G data-center switch and router reference-clock generation, replacing multiple discrete XOs with a single MultiSynth device. Its 190 fs RMS jitter directly satisfies IEEE 802.3ba 40G/100G transmitter reference-clock phase-noise masks, and 6 independently programmable outputs up to 333.33 MHz support PHY, MAC, and SERDES reference rails simultaneously. Per the Si5332 datasheet, configurable LVDS/LVPECL/HCSL output formats match common PHY/SerDes reference inputs. In a typical deployment, a 25 MHz TCXO feeds the SI5332A-D-GM1 reference input, and outputs deliver 156.25 MHz for PHY, 161.13 MHz for SERDES, and 200 MHz for FPGA fabric. Trade-off: a single device replacing 4-6 XOs reduces BOM and board area at the cost of a slight firmware burden for register configuration.
Recommended
FPGA / ASIC Reference Clock Generation
Industrial and communications FPGAs (Xilinx, Intel, Microchip) typically require multiple reference clocks - one for the fabric, one for transceivers, one for memory controllers - each at a different frequency. The SI5332A-D-GM1 generates all three from a single 2.5/3.3 V supply with 190 fs RMS jitter, well below the reference-clock requirement for 10G transceiver channels. Per the Si5332 Reference Manual, the device's MultiSynth fractional divider architecture means designers can tune frequencies in software rather than ordering custom XOs. The 32-VFQFN exposed-pad package simplifies PCB thermal management and reflow assembly. Trade-off: an I2C/SPI controller (typically a small MCU or FPGA pin) is required to program the Si5332's register map, whereas discrete XOs need no configuration.
Recommended
Multi-Channel ADC / DAC Sampling Clock Generation
High-speed ADCs and DACs require low-jitter sampling clocks because phase noise directly degrades signal-to-noise ratio (SNR) per the formula SNR = 6.02*N + 1.76 - 20*log10(2*pi*f_in*jitter_rms). The SI5332A-D-GM1's 190 fs RMS jitter translates to a >70 dB SNR floor at 100 MHz IF, making it suitable for 14-bit/16-bit ADC/DAC channels in test-and-measurement and communications systems. Six outputs let designers clock multiple converters from a single device, and the configurable LVDS/LVPECL/HCSL outputs match most modern converter clock inputs. The Si5332 datasheet emphasizes clean supply decoupling (1 uF and 0.1 uF near each VDD pin) for optimal jitter performance. Trade-off: a SI5332A-D-GM1-based design slightly exceeds a discrete-XO clock in cost, but recovers it through BOM consolidation and frequency agility.
Recommended
Test & Measurement Instrumentation
Test-and-measurement equipment (spectrum analyzers, signal generators, oscilloscopes) requires a clean, programmable clock-tree to support multiple sampling rates and trigger domains. The SI5332A-D-GM1's 5 MHz to 333.33 MHz any-frequency outputs enable a single board design to deliver reference clocks at 100 MHz for the FPGA, 300 MHz for the ADC, 10 MHz for the reference PLL, and custom rates for the front-end digitizer. With 190 fs RMS jitter, the SI5332A-D-GM1 meets or exceeds the clock-domain purity required by 12-bit/14-bit/16-bit instruments. The 32-VFQFN exposed-pad package simplifies thermal management in enclosed chassis. Trade-off: the SI5332A-D-GM1 is overkill for a single-frequency, low-precision instrument, but pays for itself in any multi-domain or wideband design.
Recommended
PCI Express Reference Clock Generation
PCIe Gen 2/3/4 systems require a 100 MHz HCSL reference clock with strict phase-noise and SSC tolerance. The SI5332A-D-GM1 generates 100 MHz HCSL directly on its configurable outputs, satisfying PCIe CEM specification requirements. Six outputs enable a single device to clock a PCIe switch, endpoint, and clock buffer chain. Per the Si5332 Reference Manual, spread-spectrum clocking (SSC) is supported via hardware pins or register programming for PCIe applications that mandate down-spread SSC. The 32-VFQFN exposed-pad package supports standard reflow profiles. Trade-off: PCIe Gen 5 requires tighter jitter than the SI5332A-D-GM1's 190 fs RMS guarantees; for Gen 5 designs, consider Si5332 family members with explicitly rated PCIe Gen 5 jitter.
Recommended
Industrial Mixed-Voltage Clock Distribution
Industrial designs frequently require different logic-level clocks (1.8 V, 2.5 V, 3.3 V) feeding different ASIC subsystems. Per the Si5332 datasheet, the SI5332A-D-GM1 supports multiple output-voltage banks so each of the six outputs can drive a different voltage domain independently, eliminating level shifters and clock buffers. This mixed-supply capability, combined with 190 fs RMS jitter, makes it suitable for motor-control, industrial-Ethernet, and factory-automation PCBs that combine 24V sensors, 5V MCUs, and 3.3V FPGAs. Trade-off: a multi-bank clock generator slightly exceeds a single-output XO in standby current, but recovers it through footprint reduction and design flexibility.
Recommended
Recommended Products Summary
Engineering reference data for SI5332A-D-GM1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5332A-D-AM1 | SI5332B-D-GM1 | SI5332C-D-GM1 | SI5332D-D-GM1 | SI5332G-D-GM1 | SI5332A-D-AM2 |
|---|---|---|---|---|---|---|---|
| Package | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad | 32-VFQFN Exposed Pad |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 6 | 6 | 6 | 6 | 6 | 12 | 6 |
| Output Frequency Range | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz | 5 MHz to 333.33 MHz |
| Output Jitter (RMS) | 190 fs | 190 fs | 190 fs | 190 fs | 190 fs | 190 fs | 190 fs |
| Divider Architecture | MultiSynth INT+FRAC | MultiSynth INT+FRAC | MultiSynth INT+FRAC | MultiSynth INT+FRAC | MultiSynth INT+FRAC | MultiSynth INT+FRAC | MultiSynth INT+FRAC |
| Output Format | LVDS/LVPECL/HCSL/CMOS configurable | LVDS/LVPECL/HCSL/CMOS | LVDS/LVPECL/HCSL/CMOS | LVDS/LVPECL/HCSL/CMOS | LVDS/LVPECL/HCSL/CMOS | LVDS/LVPECL/HCSL/CMOS | LVDS/LVPECL/HCSL/CMOS |
| Programming Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
Key Differentiators
- 6 independently programmable any-frequency outputs from a single MultiSynth device (vs Discrete crystal-oscillator array (4-6 separate XOs))
- 190 fs RMS jitter, among the lowest in class (vs Discrete 25 MHz TCXO + buffer)
- Configurable output formats (LVDS/LVPECL/HCSL/CMOS) per output (vs Fixed-format clock generator (e.g., CDCE937))
Design Notes
Follow the Skyworks Si5332 Reference Manual PCB layout for the crystal interface. Place the crystal as close as possible to the XA/XB pins, route XA and XB symmetrically with matched length (within 100 mil), and surround the crystal oscillator section with a ground ring. Keep digital traces away from XA/XB to avoid coupling noise into the reference path. The exposed pad (EP) must be soldered to the ground plane with at least 5 thermal vias to ensure lowest thermal resistance for the 32-VFQFN package.
Decouple each VDD pin with a 1 uF X7R ceramic capacitor in parallel with a 0.1 uF X7R ceramic, placed as close to the pin as possible. Use separate ferrite beads or pi-filters to isolate VDD_DIG and VDD_XTAL from the analog VDD. Per the Si5332 datasheet, supply noise directly multiplies into output jitter, so clean supplies are essential to achieve the 190 fs RMS specification. Use a low-noise LDO (such as the TPS7A4701) for the VDD rail feeding the Si5332 in noise-sensitive applications.
For differential outputs (LVDS/LVPECL/HCSL), route the OUTn and OUTn_N pair as a matched-impedance differential pair with 100 ohm differential impedance, keep pairs at equal length (within 5 mil), and avoid right-angle bends. Minimize via count in the output path - each via adds ~1 nH of discontinuity. For CMOS outputs, place a 33 ohm series-termination resistor close to the driver pin to damp reflections on long traces. Match trace length to within 1/10 of the rise time to avoid timing skew between outputs.
Do not omit the external crystal load capacitors specified in Table 5.4 of the Si5332 datasheet - missing or wrong-value caps cause frequency error and degraded jitter. Do not program non-default output frequencies without first loading a valid register map from the Si5332 ClockBuilder Pro configuration tool. Reset the device (RESET pin low, then high) after VDD stabilizes for at least 1 ms before I2C/SPI access. Mixing incompatible Si5332 family register maps (e.g., A-variant map on a C-variant device) can lock up the I2C interface.
Compliance Information
RoHS compliant per Skyworks product page. Not AEC-Q100 qualified - the Si5332A-D-GM1 targets industrial and communications markets, not automotive.
