SI5341A-D07228-GM - 10-Output Ultra-Low Jitter Clock Gen | Skyworks
MPN: SI5341A-D07228-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.62 | $256.20 |
| 100 | $22.74 | $2,274.00 |
| 500 | $20.45 | $10,225.00 |
| 1,000 | $18.92 | $18,920.00 |
SI5341A-D07228-GM Overview
An any-frequency, any-output clock generator is a programmable timing IC that synthesizes arbitrary integer and non-integer related frequencies from a single reference. It belongs to the clock generator hierarchy: clock generator -> PLL/synthesizer -> timing IC -> semiconductor. By replacing multiple crystal oscillators with one programmable device, it enables design flexibility, BOM consolidation, and reduced board area for complex multi-clock systems used in communications infrastructure, broadcast video, and high-speed data conversion.
Key features include 90 fs RMS ultra-low jitter, ten independently programmable outputs, integrated MultiSynth fractional-N blocks, and built-in holdover capability. The Si5341A-D07228-GM operates from a 1.71 V to 3.47 V supply, offers selectable LVDS, LVPECL, HCSL, and LVCMOS output formats, and integrates an EEPROM for autonomous configuration. It supports Glitchless output muting and per-output phase adjustment, which simplifies PCB layout in dense multi-clock domains.
Architecturally, the Si5341A-D07228-GM combines a wide-band integer PLL that locks to an external reference with up to five MultiSynth fractional divider blocks that each independently synthesize non-integer related output frequencies. This dual-stage architecture avoids the spurs typical of single-loop fractional-N synthesizers while keeping frequency flexibility. Register-only configuration uses an I2C or SPI serial interface, and optional non-volatile configuration via on-chip EEPROM allows standalone boot without a host controller.
Typical applications include wireless base station timing, broadcast video reference clock generation, high-speed ADC/DAC sampling clocks, FPGA/ASIC reference and fabric clocks, OTN/SONET/SDH line cards, and server/storage timing. In all these roles, the Si5341A's 90 fs jitter preserves signal integrity in high-speed serial links and tight SNR budgets. When designing with this device, allocate a 64-pin 9 mm × 9 mm QFN footprint with a sufficient thermal via array under the exposed pad to keep junction temperature within range. A high-isolation multi-layer stack-up with split analog/digital ground is recommended because the part is sensitive to power-supply noise on the PLL supply rails. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not found in the manufacturer datasheet alone.
Drop-in alternatives for SI5341A-D07228-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5341A-D07228-GM (same form factor and footprint) — differing in Package, Number of Outputs, Function, Output Formats, Maximum Output Frequency.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5341A-D-GM
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →SI5341A-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5340A-D-GM
✅ Drop-In✓ In Stock
$14.75 / Unit
View Datasheet →SI5341B-D-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341A-D07228-GM Specifications
| Product Type | Any-frequency, any-output clock generator |
| Number of Outputs | 10 (programmable) |
| Maximum Output Frequency | 1028 MHz |
| Output Jitter | 90 fs RMS (12 kHz to 20 MHz) |
| Supply Voltage Range | 1.71 V to 3.47 V |
| Reference Input - Crystal | 25 MHz to 54 MHz |
| Reference Input - Differential Clock | 10 MHz to 750 MHz |
| Reference Input - LVCMOS Clock | 10 MHz to 250 MHz |
| Output Formats | LVDS / LVPECL / HCSL / LVCMOS |
| Configuration Interface | I2C / SPI |
| On-chip Configuration Memory | Yes (EEPROM) |
| Package | 64-pin VFQFN exposed-pad (QFN-64) |
| Package Dimensions | 9 mm x 9 mm |
| Operating Temperature Range | -40 C to +85 C |
| Mounting Type | Surface Mount |
| MultiSynth Fractional Synthesizer | Yes (proprietary) |
| RoHS Status | Compliant |
SI5341A-D07228-GM Pin Configuration
| Pin 1 | IN0 — Reference clock input 0 (differential/single-ended) |
| Pin 2 | IN1 — Reference clock input 1 (differential/single-ended) |
| Pin 3 | XA — Crystal oscillator input A |
| Pin 4 | XB — Crystal oscillator input B |
| Pin 5 | VDDA — Analog supply voltage (1.8 V or 3.3 V) |
| Pin 6 | VDDA — Analog supply voltage (1.8 V or 3.3 V) |
| Pin 7 | GND — Ground |
| Pin 8 | VDD_DIG — Digital core supply voltage |
| Pin 9 | SDA — I2C data (or SPI MISO) |
| Pin 10 | SCL — I2C clock (or SPI SCLK) |
| Pin 11 | CS — SPI chip select (I2C address strap in I2C mode) |
| Pin 12 | RST — Device reset (active low) |
| Pin 13 | OUT0A — Clock output 0 positive (programmable format) |
| Pin 14 | OUT0B — Clock output 0 negative |
| Pin 15 | VDDO0 — Output supply for bank 0 |
| Pin 16 | GND — Ground |
| Pin 17 | OUT1A — Clock output 1 positive |
| Pin 18 | OUT1B — Clock output 1 negative |
| Pin 19 | VDDO1 — Output supply for bank 1 |
| Pin 20 | GND — Ground |
| Pin 21 | OUT2A — Clock output 2 positive |
| Pin 22 | OUT2B — Clock output 2 negative |
| Pin 23 | VDDO2 — Output supply for bank 2 |
| Pin 24 | GND — Ground |
| Pin 25 | OUT3A — Clock output 3 positive |
| Pin 26 | OUT3B — Clock output 3 negative |
| Pin 27 | VDDO3 — Output supply for bank 3 |
| Pin 28 | GND — Ground |
| Pin 29 | OUT4A — Clock output 4 positive |
| Pin 30 | OUT4B — Clock output 4 negative |
| Pin 31 | VDDO4 — Output supply for bank 4 |
| Pin 32 | GND — Ground |
| Pin 33 | OUT5A — Clock output 5 positive |
| Pin 34 | OUT5B — Clock output 5 negative |
| Pin 35 | VDDO5 — Output supply for bank 5 |
| Pin 36 | GND — Ground |
| Pin 37 | OUT6A — Clock output 6 positive |
| Pin 38 | OUT6B — Clock output 6 negative |
| Pin 39 | VDDO6 — Output supply for bank 6 |
| Pin 40 | GND — Ground |
| Pin 41 | OUT7A — Clock output 7 positive |
| Pin 42 | OUT7B — Clock output 7 negative |
| Pin 43 | VDDO7 — Output supply for bank 7 |
| Pin 44 | GND — Ground |
| Pin 45 | OUT8A — Clock output 8 positive |
| Pin 46 | OUT8B — Clock output 8 negative |
| Pin 47 | VDDO8 — Output supply for bank 8 |
| Pin 48 | GND — Ground |
| Pin 49 | OUT9A — Clock output 9 positive |
| Pin 50 | OUT9B — Clock output 9 negative |
| Pin 51 | VDDO9 — Output supply for bank 9 |
| Pin 52 | GND — Ground |
| Pin 53 | GPIO0 — General-purpose I/O 0 (status/control) |
| Pin 54 | GPIO1 — General-purpose I/O 1 |
| Pin 55 | GPIO2 — General-purpose I/O 2 |
| Pin 56 | GPIO3 — General-purpose I/O 3 |
| Pin 57 | I2C_SEL — I2C/SPI mode select strap |
| Pin 58 | A0 — I2C address LSB strap |
| Pin 59 | VDD_DIG — Digital core supply |
| Pin 60 | VDDA — Analog supply |
| Pin 61 | GND — Ground |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
Typical Applications
SI5341A-D07228-GM is suitable for 6 applications: Wireless Base Station Timing, Broadcast Video Reference Clock Generation, High-Speed ADC/DAC Sampling Clock, FPGA/ASIC Reference and Fabric Clocks, OTN/SONET/SDH Line Card Timing, Server and Storage Timing.
Wireless Base Station Timing
The SI5341A-D07228-GM is an excellent fit for 4G/5G base-station timing because its 90 fs RMS jitter preserves EVM on RF data converters and serial fronthaul links. With ten programmable outputs the part replaces up to ten discrete crystal oscillators that would otherwise be needed for LTE, GPS, and baseband clocking. MultiSynth fractional-N dividers allow non-integer related frequencies (e.g. 122.88 MHz, 245.76 MHz, 30.72 MHz) from a single 38.88 MHz reference. Reference-design-grade PSRR keeps phase noise flat across -40 C to +85 C ambient swings typical of outdoor radio units.
Recommended
Broadcast Video Reference Clock Generation
In SDI, HDMI, and SMPTE 2022 broadcast video systems, the SI5341A-D07228-GM provides the 148.5 MHz and 148.35 MHz reference clocks required for 3G/HD/SD SDI serializers. Its 90 fs RMS phase jitter is well under the SMPTE 259/292/424 jitter masks, ensuring clean eye diagrams on long 75 ohm cable runs. The ten outputs simultaneously serve multiple video processors, audio clocks, and FPGA transceivers, reducing board area. Programmable output formats (LVDS, LVPECL, HCSL, LVCMOS) allow direct drive of diverse PHY inputs without level translators.
Recommended
High-Speed ADC/DAC Sampling Clock
The SI5341A-D07228-GM drives the sampling clock inputs of JESD204B/C ADC and DAC converters where aperture-jitter directly limits SNR. With 90 fs RMS additive jitter, it adds negligible phase noise to converters such as 16-bit, 1 GSPS ADCs (preserving >75 dBFS SNR) and 14-bit, 2.5 GSPS DACs. Independent output dividers allow the same device to generate the JESD204B SYSREF pulse (e.g. 7.68 MHz) and the device clock (e.g. 245.76 MHz) with deterministic phase alignment, simplifying PCB layout and saving a dedicated SYSREF generator.
Recommended
FPGA/ASIC Reference and Fabric Clocks
FPGA and ASIC designs require multiple independent clock domains: transceiver reference clocks (e.g. 156.25 MHz for 10G Ethernet), fabric clocks (e.g. 200 MHz), memory clocks (e.g. 266 MHz), and processor clocks. The SI5341A-D07228-GM provides ten independently programmable outputs from a single device, replacing a stack of fixed-frequency oscillators. The on-chip EEPROM enables standalone boot without a host controller, while the I2C/SPI interface allows post-boot dynamic frequency scaling for power-saving modes. Its 90 fs jitter keeps transceiver eye diagrams open at 25.78125 Gbps.
Recommended
OTN/SONET/SDH Line Card Timing
Optical transport network line cards demand strict jitter compliance to ITU-T G.8251 and Telcordia GR-253. The SI5341A-D07228-GM provides the 155.52 MHz, 311.04 MHz, and 622.08 MHz rates required for OTU1/OTU2 with phase noise well inside the masks. Ten outputs serve line-side, client-side, and backplane SERDES simultaneously. Holdover and hitless reference switching capability allow the line card to ride through brief reference losses without resetting the PHY, which is critical for carrier-grade reliability.
Recommended
Server and Storage Timing
In SATA/SAS/NVMe storage and PCIe Gen4/Gen5 server backplanes, the SI5341A-D07228-GM delivers the 100 MHz reference clocks required by PCIe, SATA, and SAS PHYs with sub-100 fs jitter that exceeds the PCIe CEM jitter tolerance. The 64-pin VFQFN package fits standard server PCB stack-ups, and its 1.8 V operation supports modern low-voltage server power rails. Multiple outputs allow a single device to clock a switch ASIC, multiple NVMe controllers, and a BMC, reducing component count.
Recommended
Recommended Products Summary
Engineering reference data for SI5341A-D07228-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5341A-D-GM | SI5341A-B-GM | SI5340A-D-GM | SI5341B-D-GM |
|---|---|---|---|---|---|
| Package | 64-pin VFQFN exposed pad | 64-pin VFQFN exposed pad - same | 64-pin VFQFN exposed pad - same | 64-pin VFQFN exposed pad - same | 64-pin VFQFN exposed pad - same |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Output Jitter (RMS) | 90 fs | 90 fs | 130 fs (~30% higher) | 90 fs | 90 fs |
| Number of Outputs | 10 | 10 | 10 | 4 (-60%) | 10 |
| Maximum Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Supply Voltage | 1.71 V to 3.47 V | 1.71 V to 3.47 V | 1.71 V to 3.47 V | 1.71 V to 3.47 V | 1.71 V to 3.47 V |
| Pre-programmed Frequency Plan | Yes (D07228 code) | No (default) | No (default) | No (default) | No (default) |
| Silicon Revision | Rev A | Rev A | Rev A (B-grade) | Rev A | Rev B |
Key Differentiators
- Pre-programmed factory frequency plan (vs SI5341A-D-GM)
- Lowest jitter in the Si5341 family (A grade) (vs SI5341A-B-GM)
- Ten fully independent programmable outputs (vs SI5340A-D-GM)
Design Notes
Provide separate decoupling for VDDA (analog PLL supply) and VDDD/VVDD_DIG (digital core) on the SI5341A-D07228-GM. Place a 10 uF bulk plus 0.1 uF and 1 nF ceramic capacitors within 2 mm of each supply pin, with the 1 nF cap closest to the IC. Power the analog and digital domains from filtered LDO outputs to keep PLL phase noise within datasheet limits. Estimate: at 200 mA typical IDD, the device dissipates roughly 0.4 W on a 1.8 V supply, which is easily handled by the 64-pin QFN thermal pad.
The 64-pin VFQFN exposed pad is the primary thermal and ground return path. Place a continuous ground plane on the top layer under the package, with at least a 5 x 5 array of 0.3 mm thermal vias stitching the top pad to inner ground planes. Keep differential output traces length-matched to within 5 mil (0.13 mm) and impedance-controlled at 100 ohm differential (LVDS/HCSL) or 85 ohm differential (LVPECL). Reference Skyworks application note AN1173 for stack-up and via recommendations.
Route output clocks away from switching power converters and high-speed digital buses. Use guard traces or coplanar waveguide with ground stitching vias every 5 mm to contain radiated EMI. Place series termination resistors at the driver output (typically 33 ohm for LVDS, 220 ohm for LVPECL at the receiver). For multi-load LVCMOS clock trees, switch to lower-frequency outputs or a fanout buffer (e.g. SI5338 family) to avoid loading the Si5341A outputs beyond their 30 pF drive spec.
Do not skip the I2C/SPI address straps (CS and A0): the SI5341A powers up with default settings and requires a frequency plan to be loaded before outputs become valid. Hold RST low during power ramp until supplies stabilize. Avoid using both LVCMOS and differential outputs from the same bank simultaneously - they share VDDO rails and the voltage may need to match. Finally, regenerate the frequency plan with ClockBuilder Pro whenever the input reference frequency changes; field firmware edits to the header file are unsupported.
Compliance Information
RoHS, REACH, and PFIS status confirmed on Skyworks product page (skyworksinc.com/en/products/timing/ultra-low-jitter-clock-generators/si5341a). Industrial -40 C to +85 C grade; not AEC-Q100 qualified.
