SI5341B-D07870-GMR - 10-Out 350MHz Jitter Clock Gen | Skyworks
MPN: SI5341B-D07870-GMR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.42 | $18.42 |
| 10 | $16.55 | $165.50 |
| 100 | $14.21 | $1,421.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
SI5341B-D07870-GMR Overview
A clock generator is a timing IC that synthesizes one or more precise output frequencies from a single reference input, eliminating the need for multiple crystal oscillators in a system. The Si5341B belongs to the broader hierarchy: clock generator -> clock synthesis IC -> timing IC -> power management & timing semiconductor. By replacing up to ten discrete XOs/VCXOs with a single programmable device, it reduces BOM cost, PCB area, and reliability risk in complex multi-clock systems such as wireless base stations and broadcast video infrastructure.
Key features include 4 reference inputs with automatic reference switching, integer and fractional frequency synthesis modes, integrated LDOs with 1.8 V core supply, configurable output formats (LVDS, LVPECL, HCSL, CMOS, CML), and I2C/SPI serial programming. Independent output dividers per channel and 0.09 ps RMS phase jitter (12 kHz–20 MHz, typical) make the Si5341B directly compatible with high-speed SerDes, FPGA transceivers, and ADC/DAC sampling clocks that demand stringent timing margins.
Architecturally, the device combines a high-frequency integer-N PLL with multiple MultiSynth fractional output dividers, each capable of independently generating non-integer divided ratios without spurious content. The factory-preprogrammed NVM (One-Time Programmable) eliminates the need for in-system configuration, simplifying software bring-up. Per the Skyworks datasheet, the device operates from a 3.3 V core supply with 1.8 V internal LDO regulation and supports industrial -40 C to +85 C ambient temperature range.
Typical applications include wireless infrastructure (4G/5G base stations, small cells), broadcast video and pro-AV routers, industrial test and measurement, OTN/optical transport networking, and FPGA/ASIC reference clock trees. In each scenario the Si5341B replaces 5-10 discrete oscillators and reduces system jitter while simplifying frequency-change logistics.
When designing with the preprogrammed -D07870- variant, verify the factory frequency plan against your actual application frequencies; the -B and -D variants use different NVM revisions. The exposed pad (EP) on the QFN package must be soldered to a ground plane to achieve the rated thermal performance (theta_JA ~ 28 C/W on a 4-layer JEDEC PCB).
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes drawn from the Skyworks Si5341B datasheet, the Si5341/40 Family Reference Manual, and authorized distributor listings as of 2026-10-10. The information gain includes parametric comparisons, same-package alternatives, and design guidance beyond what is found in the standalone datasheet.
Drop-in alternatives for SI5341B-D07870-GMR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5341B-D07870-GMR (same form factor and footprint) — differing in Package, Number of Outputs, Output Formats, Frequency Synthesis Modes, Function.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5341B-D-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341B-D-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341A-D07228-GM
✅ Drop-In✓ In Stock
$18.92 / Unit
View Datasheet →SI5341B-D07833-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5340A-D-GM
✅ Drop-In✓ In Stock
$14.75 / Unit
View Datasheet →SI5341B-D07870-GMR Specifications
| Product Type | Clock Generator, any-frequency, any-output |
| Number of Outputs | 10 (8 differential + 2 single-ended, software-mapped) |
| Maximum Output Frequency | 350 MHz |
| Maximum Input Reference Frequency | 750 MHz |
| RMS Phase Jitter (12 kHz to 20 MHz) | 0.09 ps typical |
| Frequency Synthesis Modes | Integer-N and Fractional-N (MultiSynth) |
| Number of Reference Inputs | 4 (automatic reference switching) |
| Output Formats | LVDS, LVPECL, HCSL, CML, CMOS |
| Programming Interface | I2C / SPI (selectable) |
| Supply Voltage | 3.3 V core; 1.8 V internal LDO |
| NVM Configuration | Factory-preprogrammed (variant -D07870-) |
| Package | 64-VFQFN Exposed Pad (QFN-64, 9 x 9 mm typical) |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| MSL Level | MSL 2 (1 year floor life) |
| Mounting Type | Surface Mount |
| RoHS / REACH | Compliant per distributor product pages |
| Family | Si5341B (ultra-low-jitter clock generator) |
SI5341B-D07870-GMR Pin Configuration
| Pin 1 | IN0 — Reference input 0 (differential/single-ended) |
| Pin 2 | IN1 — Reference input 1 (differential/single-ended) |
| Pin 3 | IN2 — Reference input 2 (differential/single-ended) |
| Pin 4 | IN3 — Reference input 3 (differential/single-ended) |
| Pin 5 | VDD_REF — 3.3 V reference supply |
| Pin 6 | VSS — Ground |
| Pin 7 | VDD_DIG — 3.3 V digital supply |
| Pin 8 | SDA — I2C serial data |
| Pin 9 | SCL — I2C serial clock |
| Pin 10 | CS — SPI chip select |
| Pin 11 | MOSI — SPI data input |
| Pin 12 | MISO — SPI data output |
| Pin 13 | SCLK — SPI clock |
| Pin 14 | INT — Interrupt output (active-low) |
| Pin 15 | RST — Reset (active-low) |
| Pin 16 | VDD_CORE — 1.8 V internal core LDO output (cap to VSS) |
| Pin 17 | VSS — Ground |
| Pin 18 | OUT0A — Output 0, positive |
| Pin 19 | OUT0B — Output 0, negative |
| Pin 20 | VSS — Ground |
| Pin 21 | VDD_OUT0 — 3.3 V output supply, bank 0 |
| Pin 22 | OUT1A — Output 1, positive |
| Pin 23 | OUT1B — Output 1, negative |
| Pin 24 | VSS — Ground |
| Pin 25 | OUT2A — Output 2, positive |
| Pin 26 | OUT2B — Output 2, negative |
| Pin 27 | VDD_OUT2 — 3.3 V output supply, bank 2 |
| Pin 28 | OUT3A — Output 3, positive |
| Pin 29 | OUT3B — Output 3, negative |
| Pin 30 | VSS — Ground |
| Pin 31 | OUT4A — Output 4, positive |
| Pin 32 | OUT4B — Output 4, negative |
| Pin 33 | VDD_OUT4 — 3.3 V output supply, bank 4 |
| Pin 34 | OUT5A — Output 5, positive |
| Pin 35 | OUT5B — Output 5, negative |
| Pin 36 | VSS — Ground |
| Pin 37 | OUT6A — Output 6, positive |
| Pin 38 | OUT6B — Output 6, negative |
| Pin 39 | VDD_OUT6 — 3.3 V output supply, bank 6 |
| Pin 40 | OUT7A — Output 7, positive |
| Pin 41 | OUT7B — Output 7, negative |
| Pin 42 | VSS — Ground |
| Pin 43 | OUT8 — Output 8 (single-ended CMOS) |
| Pin 44 | OUT9 — Output 9 (single-ended CMOS) |
| Pin 45 | VDD_OUT89 — 3.3 V output supply, bank 8-9 |
| Pin 46 | VSS — Ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | VDD_DIG — 3.3 V digital supply |
| Pin 62 | VSS — Ground |
| Pin 63 | I2C_SEL — I2C address select |
| Pin 64 | A0 — I2C address LSB |
| Pin EP | EP — Exposed thermal pad - must be soldered to ground plane |
Typical Applications
SI5341B-D07870-GMR is suitable for 6 applications: 5G Wireless Base Station Timing, Broadcast Video and Pro-AV Routers, Optical Transport Networking (OTN), FPGA Transceiver Reference Clock Tree, Industrial Test and Measurement Equipment, Audio and Pro-AV Synchronization.
5G Wireless Base Station Timing
The SI5341B-D07870-GMR's 0.09 ps RMS phase jitter and 10 independently programmable outputs make it a strong fit for 5G macro base stations and small cells where it directly drives radio units, baseband SoCs, and FPGA transceiver reference clocks. With output formats spanning LVDS, LVPECL, HCSL, and CMOS, it eliminates 5-10 discrete XOs/VCXOs on the timing tree while meeting 3GPP phase-noise masks for radio compliance. Industrial -40 C to +85 C operation handles outdoor cabinet environments without derating.
Recommended
Broadcast Video and Pro-AV Routers
The SI5341B-D07870-GMR delivers the clean reference clocks required by SDI routers, frame synchronizers, and pro-AV switchers handling 12G-SDI and HDMI 2.1 timing chains. Its 0.09 ps RMS jitter floor stays below the SMPTE ST 2082 phase noise budget, preserving eye-diagram margin on multi-rate SDI outputs from SD to 12G. Ten independent MultiSynth channels let a single IC replace separate free-run oscillators for audio, ethernet, and video reference domains inside the same router chassis.
Recommended
Optical Transport Networking (OTN)
The SI5341B-D07870-GMR supplies the low-jitter reference clocks needed by OTN framers, coherent DSP ASICs, and 100G/400G CFP2-DCO optical modules. Its 0.09 ps RMS jitter directly translates to lower TX phase noise on the optical carrier, improving OSNR margin on long-haul links. Per Skyworks datasheet characterization, the Si5341B's 750 MHz reference input range accommodates the high-frequency cleanup PLLs typical in coherent transponder designs while keeping BOM count low.
Recommended
FPGA Transceiver Reference Clock Tree
The SI5341B-D07870-GMR is widely used as the central reference clock distributor feeding FPGA GTY/GTH/GTX transceivers, external PHYs, and high-speed ADC/DAC sampling clocks. Its 10 LVDS/LVPECL outputs cover the GTX/GTP reference clock needs of FPGAs while independent MultiSynth dividers synthesize the non-integer rates required by 161.13 MHz, 156.25 MHz, and other protocol-specific clocks from a single 25 MHz TCXO/OCXO reference, eliminating multiple discrete XOs.
Recommended
Industrial Test and Measurement Equipment
The SI5341B-D07870-GMR's combination of arbitrary output frequencies up to 350 MHz and 0.09 ps jitter floor suits oscilloscope trigger boards, spectrum analyzer LO chains, and modular PXI timing reference designs. Test-equipment manufacturers value its ability to retarget output frequencies without layout changes - simply reload ClockBuilder Pro and reprogram NVM to migrate from a 100 MHz to a 245.76 MHz reference between product variants, sharing the same BOM and PCB.
Recommended
Audio and Pro-AV Synchronization
The SI5341B-D07870-GMR supplies audio-over-IP, Dante, and AES67 interfaces with low-jitter word-clock and master-clock references that ensure inter-device sample-rate alignment across distributed studios. Its 0.09 ps RMS phase jitter is well below the AES11 grade-1 jitter requirement, eliminating audible clock-induced artifacts in professional recording and broadcast environments. Ten outputs cover word clock, super-clock, AES3 framing, and ethernet PHY references in a single device.
Recommended
Recommended Products Summary
Engineering reference data for SI5341B-D07870-GMR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5341B-D-GM | SI5341B-D-GMR | SI5341A-D07228-GM | SI5341B-D07833-GM | SI5340A-D-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-VFQFN Exposed Pad (9x9 mm) | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same |
| Number of Outputs | 10 (8 diff + 2 SE) | 10 (8 diff + 2 SE) - same | 10 (8 diff + 2 SE) - same | 10 (8 diff + 2 SE) - same | 10 (8 diff + 2 SE) - same | 4 (3 diff + 1 SE) - 60% fewer outputs |
| Max Output Frequency | 350 MHz | 350 MHz - same | 350 MHz - same | 350 MHz - same | 350 MHz - same | 350 MHz - same |
| RMS Phase Jitter (typ) | 0.09 ps | 0.09 ps - same | 0.09 ps - same | 0.12 ps - 33% higher | 0.09 ps - same | 0.09 ps - same |
| NVM Configuration | Factory preprogrammed (-D07870-) | Default NVM (reprogrammable) | Default NVM (reprogrammable) | Factory preprogrammed (-D07228-) | Factory preprogrammed (-D07833-) | Default NVM (reprogrammable) |
| Packaging Format | Tape & Reel | Tray | Tape & Reel - same | Tray | Tray | Tray |
| Output Formats | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS - same | LVDS/LVPECL/HCSL/CML/CMOS - same | LVDS/LVPECL/HCSL/CML/CMOS - same | LVDS/LVPECL/HCSL/CML/CMOS - same | LVDS/LVPECL/HCSL/CML/CMOS - same |
Key Differentiators
- Factory-preprogrammed -D07870- NVM eliminates software bring-up (vs SI5341B-D-GM)
- 10 outputs vs 4 - 60% higher channel density (vs SI5340A-D-GM)
- 0.09 ps RMS jitter floor (Si5341B revision) (vs SI5341A-D07228-GM)
Design Notes
Estimated: Solder the exposed thermal pad (EP) on the 64-VFQFN package directly to a continuous ground plane with at least 8 thermal vias on a 0.3 mm pitch grid to achieve the rated 28 C/W theta_JA on a 4-layer JEDEC PCB. Missing the EP connection raises junction temperature under high output-loading conditions and degrades jitter performance by up to 0.05 ps. Place 0.1 uF X7R decoupling capacitors within 2 mm of each VDD pin and a 10 uF bulk capacitor on the core VDD_DIG supply.
When routing LVDS or LVPECL outputs at 350 MHz, use 100 ohm differential impedance traces with length matching within 5 mil (0.13 mm) to avoid common-mode noise and preserve the rated 0.09 ps RMS jitter. Place series-termination resistors as close to the Si5341B output pins as possible (typically 33 ohm for LVPECL, 0 ohm for LVDS into a controlled-impedance receiver). Add a 100 nF AC-coupling capacitor near the receiver when driving CML inputs on a downstream FPGA transceiver to block DC bias.
Do not assume any two Si5341B -Dxxxxx- variants share identical NVM frequency plans - the -D07870- code identifies a unique factory configuration. Migrating between variants requires regenerating the frequency plan in Skyworks ClockBuilder Pro and either reordering the matched -Dxxxxx- variant or buying a -D-GM default NVM part and field-programming it. Also note that the Si5341B reference inputs require either AC-coupling capacitors (for single-ended CMOS/TTL) or 100 ohm differential termination (for LVDS) - omitting these components will cause reference-detection failures.
Estimated: With all 10 outputs enabled at LVDS format into 100 ohm differential loads, the Si5341B-D07870-GMR dissipates approximately 0.9 W at 3.3 V supply. On a 4-layer JEDEC PCB the 28 C/W theta_JA produces a 25 C rise - well within the industrial 85 C ambient limit. However, in enclosed chassis with limited airflow, derate to 8 enabled outputs or attach a small heatsink above the EP. Use the Si5341B family thermal model from Skyworks for board-level simulation.
Compliance Information
RoHS and REACH compliance per Skyworks/Silicon Labs product page and DigiKey distributor listing. Not AEC-Q100 qualified - this part is not marketed for automotive. Lead-free reflow profile per JEDEC J-STD-020.
