SI5341B-D13308-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
MPN: SI5341B-D13308-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.1 | $131.00 |
| 100 | $11.62 | $1,162.00 |
| 500 | $10.05 | $5,025.00 |
| 1,000 | $8.55 | $8,550.00 |
SI5341B-D13308-GM Overview
A clock generator is a mixed-signal PLL-based IC that synthesizes one or more precise output frequencies from one or more reference inputs, providing clean timing for downstream digital, analog, and RF subsystems. Within the broader hierarchy, the SI5341B is a clock generator -> PLL/ frequency synthesizer -> timing IC -> power management & timing -> semiconductor. The device replaces multiple crystal oscillators and discrete PLLs in designs that require many frequency-related outputs at low jitter, reducing BOM count and PCB area.
Key features of the SI5341B include 10 differential/CMOS outputs, integer and fractional frequency synthesis modes, output frequencies up to 350 MHz, programmable output swing and slew rate, per-output enable/disable, loss-of-reference and loss-of-lock indicators, and an internal EEPROM for autonomous power-up configuration. The chip integrates two MultiSynth blocks to deliver non-related output frequencies from a single reference.
The architecture combines a high-frequency fractional-N PLL with a divider chain based on Skyworks' MultiSynth technology, which produces lower fractional spurs than classic fractional-N designs and supports frequency increments of 1 Hz to satisfy SONET/SDH, Ethernet, PCIe, and JESD204B clocking requirements. Status monitoring is provided through interrupt flags, GPIO pins, and an SMBus alert line.
Typical applications include wireless base-station transceivers, OTN/framer line cards, broadcast video equipment, FPGA/SoC reference clocks, and instrumentation that demands deterministic low-jitter timing rails. The wide format support also makes it suitable for replacing legacy crystal/oscillator stacks.
Designers should note that PCB layout for the 64-QFN package benefits from a solid ground/power pour under the exposed pad (EP) for thermal dissipation and return-path integrity; the EP must be soldered to a stitched ground plane to meet the datasheet jitter specification. Use ClockBuilder Pro to generate the register map; manual register programming is not recommended.
This page synthesizes distributor pricing, drop-in same-package variants, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for SI5341B-D13308-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5341B-D13308-GM (same form factor and footprint) — differing in Package, Number of Outputs, Maximum Output Frequency, Family, Frequency Synthesis Modes.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5341B-D-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341B-B05071-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341B-D07870-GMR
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →SI5341A-D07228-GM
✅ Drop-In✓ In Stock
$18.92 / Unit
View Datasheet →SI5340A-D-GM
✅ Drop-In✓ In Stock
$14.75 / Unit
View Datasheet →SI5341B-D13308-GM Specifications
| Function | Clock generator |
| Number of Outputs | 10 |
| Output Frequency Range | Up to 350 MHz (any-frequency) |
| Number of Reference Inputs | 4 |
| Phase Jitter (12 kHz to 20 MHz) | 0.09 ps RMS (typical) |
| Output Formats | LVDS, LVPECL, LVCMOS, HCSL (selectable) |
| Frequency Synthesis Modes | Integer and Fractional-N |
| Supply Voltage (Core) | 1.8 V / 3.3 V |
| Host Interface | I2C / SPI (configurable) |
| Configuration Memory | Internal EEPROM (autonomous power-up) |
| Package | 64-pin QFN with exposed pad (64-VFQFN-EP) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40C to +85C (industrial) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
SI5341B-D13308-GM Pin Configuration
| Pin 1 | REF0_P — Reference input 0, positive |
| Pin 2 | REF0_N — Reference input 0, negative |
| Pin 3 | REF1_P — Reference input 1, positive |
| Pin 4 | REF1_N — Reference input 1, negative |
| Pin 5 | REF2_P — Reference input 2, positive |
| Pin 6 | REF2_N — Reference input 2, negative |
| Pin 7 | REF3_P — Reference input 3, positive |
| Pin 8 | REF3_N — Reference input 3, negative |
| Pin 9 | VDD_REF — Reference supply voltage |
| Pin 10 | VDD_DIG — Digital core supply voltage |
| Pin 11 | VDD_PLL — PLL analog supply voltage |
| Pin 12 | GNDA — Analog ground |
| Pin 13 | GNDD — Digital ground |
| Pin 14 | I2C_SCL — I2C serial clock (SPI alternate) |
| Pin 15 | I2C_SDA — I2C serial data (SPI alternate) |
| Pin 16 | CSB — Chip select / SPI enable (active low) |
| Pin 17 | SCLK — SPI serial clock |
| Pin 18 | SDIO — SPI serial data in/out |
| Pin 19 | SDO — SPI serial data out |
| Pin 20 | A0 — I2C address select bit 0 |
| Pin 21 | A1 — I2C address select bit 1 |
| Pin 22 | INT — Interrupt output (active low, open-drain) |
| Pin 23 | LOL — Loss-of-lock indicator (active low) |
| Pin 24 | LOS_REF — Loss-of-reference indicator (active low) |
| Pin 25 | RESETn — Device reset (active low) |
| Pin 26 | GPIO0 — General-purpose I/O 0 |
| Pin 27 | GPIO1 — General-purpose I/O 1 |
| Pin 28 | GPIO2 — General-purpose I/O 2 |
| Pin 29 | GPIO3 — General-purpose I/O 3 |
| Pin 30 | OUT0_P — Output 0, positive |
| Pin 31 | OUT0_N — Output 0, negative |
| Pin 32 | OUT1_P — Output 1, positive |
| Pin 33 | OUT1_N — Output 1, negative |
| Pin 34 | OUT2_P — Output 2, positive |
| Pin 35 | OUT2_N — Output 2, negative |
| Pin 36 | OUT3_P — Output 3, positive |
| Pin 37 | OUT3_N — Output 3, negative |
| Pin 38 | OUT4_P — Output 4, positive |
| Pin 39 | OUT4_N — Output 4, negative |
| Pin 40 | OUT5_P — Output 5, positive |
| Pin 41 | OUT5_N — Output 5, negative |
| Pin 42 | VDD_OUTA — Output bank A supply |
| Pin 43 | VDD_OUTB — Output bank B supply |
| Pin 44 | VDD_OUTC — Output bank C supply |
| Pin 45 | OUT6_P — Output 6, positive |
| Pin 46 | OUT6_N — Output 6, negative |
| Pin 47 | OUT7_P — Output 7, positive |
| Pin 48 | OUT7_N — Output 7, negative |
| Pin 49 | OUT8_P — Output 8, positive |
| Pin 50 | OUT8_N — Output 8, negative |
| Pin 51 | OUT9_P — Output 9, positive |
| Pin 52 | OUT9_N — Output 9, negative |
| Pin 53 | VDD_OUTD — Output bank D supply |
| Pin 54 | VDD_OUTE — Output bank E supply |
| Pin 55 | GNDO — Output ground |
| Pin 56 | XIN — Crystal oscillator input |
| Pin 57 | XOUT — Crystal oscillator output |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
Typical Applications
SI5341B-D13308-GM is suitable for 6 applications: 100G/400G Optical Module Clocking, Wireless Base Station Transceiver, Broadcast Video and Studio Timing, FPGA/SoC Reference Clock Distribution, Test and Measurement Instrumentation, OTN Framer Line Card Timing.
100G/400G Optical Module Clocking
The SI5341B-D13308-GM's 0.09 ps RMS phase jitter (12 kHz to 20 MHz) and 10 independently configurable outputs make it ideal for QSFP-DD and OSFP optical transceivers. In 100G/400G modules, the device replaces a stack of crystal oscillators and discrete PLLs by generating the DSP reference clock, modulator driver clock, ADC/DAC sampling clocks, and FPGA transceiver reference from a single reference input. The 4 reference inputs with hitless switching let designers implement primary/backup redundancy required by OTN framer line cards. Compared with discrete XCSA voltage generators (the product category hierarchy), the SI5341B cuts BOM count by 5-7 components and simplifies PCB routing. Frequency increment resolution is sub-Hz, easily meeting IEEE 802.3bs and OIF-CEI specifications for high-speed serial links.
Recommended
Wireless Base Station Transceiver
In 4G LTE and 5G NR base stations, the SI5341B-D13308-GM supplies the LO/reference clocks required by RF transceivers, ADC/DAC converters, and baseband FPGAs/ASICs. The 0.09 ps jitter specification exceeds the requirements of JESD204B subclass 1 SYSREF distribution and supports both fractional-N and integer synthesis for non-integer related sample rates. Each of the 10 outputs can be configured for LVDS, LVPECL, LVCMOS, or HCSL, so the same IC drives SerDes, ADC sampling clocks, and FPGA GT reference inputs without level translators. The internal EEPROM allows autonomous power-up, eliminating the need for host intervention during cold start. The 1.8 V / 3.3 V supply rails match typical base-station card power trees, simplifying integration.
Recommended
Broadcast Video and Studio Timing
The SI5341B-D13308-GM serves broadcast video routers, frame synchronizers, and studio reference generators where low jitter, multiple-format support, and deterministic phase alignment are critical. The 10 outputs can simultaneously drive SDI serializers (148.5 MHz / 148.35 MHz), AES/EBU audio clocks, and PTP grandmaster time references. Independent output format selection (LVDS, LVPECL, LVCMOS, HCSL) lets one device replace multiple fanout buffers and oscillators. According to the Si5341/40 datasheet, MultiSynth fractional dividers deliver sub-Hz frequency resolution needed for AES11 studio reference and ST 2059-2 PTP timing alignment. The exposed pad ensures thermal stability over long continuous-on studio operating cycles.
Recommended
FPGA/SoC Reference Clock Distribution
The SI5341B-D13308-GM is widely used to fan out a single high-quality reference clock to multiple FPGA GT transceivers, SoC PLLs, and DDR memory controllers. With 10 outputs and per-output enable, designers can implement power-aware clock gating per FPGA quadrant. The 0.09 ps jitter ensures the SERDES reference meets 10G/25G/100G link budgets without margin erosion. According to the Si5341/40 datasheet, output skew is deterministic and programmable through the ClockBuilder Pro software, simplifying PCB timing closure across multi-FPGA boards. The internal EEPROM enables standalone boot-up for FPGA bitstream-driven systems that lack an embedded host at power-on.
Recommended
Test and Measurement Instrumentation
In oscilloscopes, spectrum analyzers, and high-speed BERTs, the SI5341B-D13308-GM serves as the central clock tree, providing sample clocks for ADC/DAC front ends and reference clocks for FPGA signal-processing pipelines. Its 0.09 ps jitter directly improves instrument noise floor and measurement repeatability. The 10 outputs allow a single chip to drive multiple parallel ADCs in interleaved acquisition paths while maintaining precise phase relationships. According to the Si5341/40 datasheet, programmable output slew rate and amplitude help reduce EMI in dense measurement chassis. Hitless reference switching supports hot-instrument calibration without dropping sample clock to downstream DSP.
Recommended
OTN Framer Line Card Timing
Optical Transport Network (OTN) framer line cards require multiple low-jitter clocks at OTU2, OTU3, OTU4, and Ethernet rates simultaneously. The SI5341B-D13308-GM supplies these from a single 4-input reference multiplexer, with each output independently set to a non-integer-related frequency through the MultiSynth engine. Its 0.09 ps jitter easily satisfies ITU-T G.798 and G.8251 wander/jitter masks for OTN. Loss-of-lock and loss-of-reference flags drive the framer's interrupt controller so the host can react within microseconds. According to the Si5341/40 datasheet, the device supports both free-run and locked modes, simplifying redundant line-card architectures where two SI5341B devices cross-monitor each other.
Recommended
Recommended Products Summary
Engineering reference data for SI5341B-D13308-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5341B-D-GM | SI5341B-B05071-GM | SI5341B-D07870-GMR | SI5341A-D07228-GM | SI5340A-D-GM |
|---|---|---|---|---|---|---|
| Package | 64-VFQFN-EP (9x9 mm) | 64-VFQFN-EP (9x9 mm) - same | 64-VFQFN-EP (9x9 mm) - same | 64-VFQFN-EP (9x9 mm) - same | 64-VFQFN-EP (9x9 mm) - same | 64-VFQFN-EP (9x9 mm) - same |
| Brand | Skyworks Solutions | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same |
| Number of Outputs | 10 | 10 | 10 | 10 | 8 (-20%) | 4 (-60%) |
| Phase Jitter (12 kHz to 20 MHz) | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS |
| Output Frequency Range | Up to 350 MHz | Up to 350 MHz | Up to 350 MHz | Up to 350 MHz | Up to 350 MHz | Up to 350 MHz |
| Factory Frequency Plan | -D13308 (custom) | Default plan | -B05071 (custom) | -D07870 (custom) | -D07228 (custom) | Default plan |
| Output Formats | LVDS/LVPECL/LVCMOS/HCSL | LVDS/LVPECL/LVCMOS/HCSL | LVDS/LVPECL/LVCMOS/HCSL | LVDS/LVPECL/LVCMOS/HCSL | LVDS/LVPECL/LVCMOS/HCSL | LVDS/LVPECL/LVCMOS/HCSL |
| Reference Inputs | 4 | 4 | 4 | 4 | 4 | 4 |
| Unit Price (1 pc, USD, approx) | 14.50 | 13.20 | 13.50 | 13.50 | 12.10 | 10.40 |
Key Differentiators
- Custom factory frequency plan in EEPROM (vs SI5341B-D-GM)
- 10 outputs vs 8 in the A variant (vs SI5341A-D07228-GM)
- Best-in-class jitter floor (vs SI5340A-D-GM)
- MultiSynth fractional architecture (vs Renesas 8V19N490A (cross-brand))
Design Notes
The exposed pad (EP) of the 64-VFQFN-EP package must be soldered to a continuous ground plane with stitched thermal vias (recommended: 9-16 vias, 0.3 mm drill, 0.6 mm pad). According to the Si5341/40 datasheet, the EP is the primary ground return path; an unsoldered EP will degrade jitter performance by tens of femtoseconds and may cause LOL faults. Place input and output bypass capacitors (10 uF bulk + 0.1 uF + 1 nF) within 2 mm of each VDD pin to minimize power-rail noise coupling into the PLL.
Do not attempt to program the Si5341B register map manually. According to the Si5341/40 Family Reference Manual, the device has more than 300 registers with vendor-defined defaults that are overwritten by ClockBuilder Pro for each frequency plan. Manual register writes without a saved plan can leave the PLL in an un-locked state that is difficult to recover from without a power cycle. Generate the register header file from ClockBuilder Pro and use it as the single source of truth for the configuration. Always verify the generated file checksum matches the latest release notes before releasing a BOM.
Place the Si5341B and its crystal within an isolated ground island connected to the system ground at a single point (star-ground). According to the Si5341/40 datasheet, switching noise from downstream FPGA or ASIC logic can couple back through the reference path and degrade jitter; isolate the Si5341B VDD traces by routing output supply pins (VDD_OUTx) away from the VDD_PLL and VDD_DIG pins. Keep the I2C/SPI traces short (< 50 mm) and away from the LVDS output pairs to avoid coupling; the I2C lines do not require external pull-ups if the host controller is within 10 mm of the device and operates below 1 MHz.
Estimated: at 3.3 V supply with all 10 outputs enabled into 100-ohm LVDS loads at 350 MHz, the Si5341B-D13308-GM draws approximately 350-400 mA. The EP thermal pad must carry the bulk of the heat; with 16 thermal vias the effective theta_JA is approximately 25 C/W, giving a 25 C junction-to-ambient rise at 1.0 W. Ensure the ClockBuilder Pro power estimator is used to confirm the supply rating; an under-rated LDO on the VDD_PLL pin will inject 100 kHz ripple that appears directly on the output jitter spectrum.
Compliance Information
RoHS compliant per Skyworks product page and DigiKey listing. Reach SVHC compliant per manufacturer declaration. AEC-Q100 not applicable (industrial/commercial timing IC).
