SJA1105SELY - 5-Port AVB/TSN Automotive Ethernet Switch | NXP
MPN: SJA1105SELY ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.45 | $12.45 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.95 | $7,950.00 |
SJA1105SELY Overview
An automotive Ethernet switch is a specialized Layer-2 networking IC that interconnects multiple ECUs (Electronic Control Units) inside a vehicle, falling within the hierarchy of Ethernet switch -> network switch -> communication IC -> semiconductor. The SJA1105 family extends NXP's earlier SJA1105EL/TEL devices with hardened security features, frame listing (whitelisting), and wider interface options including RGMII/SGMII for gigabit uplinks. The switch core implements a 5-port store-and-forward architecture with MAC table management, VLAN processing, and cut-through forwarding.
Key features of the SJA1105SELY include 1 Gbit/s per port line rate, integrated AVB/TSN hardware timestamping, hardware-accelerated security (frame listing / MAC authentication), 1.65V-3.6V I/O flexibility for legacy 3.3V PHY compatibility, and AEC-Q100 Grade 2 automotive qualification. The LFBGA-159 package with 12x12 mm body enables compact gateway and domain controller PCB placement. SPI host interface allows the application MCU to program forwarding tables, VLAN configuration, and QoS policies at boot.
Typical applications include automotive zonal/gateway ECUs, ADAS sensor aggregation, in-vehicle infotainment backbones, body controller domain networks, and industrial TSN bridges. The combination of gigabit throughput and AVB/TSN scheduling makes it the de-facto Ethernet switch for next-generation SDV (software-defined vehicle) architectures.
Design considerations: drive the SPI host lines from a low-impedance MCU GPIO source and place the LFBGA-159 decoupling capacitors within 2 mm of the supply balls. The device is pin-compatible with the SJA1105PEL/QEL/REL/SEL family - PCBs can be reworked to support any variant without trace changes.
This page synthesizes distributor pricing, pin-compatible NXP family alternatives (SJA1105PELY, SJA1105QELY, SJA1105RELY), and practical design notes not consolidated in any single manufacturer document.
Drop-in alternatives for SJA1105SELY — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SJA1105SELY (same form factor and footprint) — differing in Function.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SJA1105PELY
✅ Drop-In📋 Reference alternative (not in catalog)
SJA1105QELY
✅ Drop-In📋 Reference alternative (not in catalog)
SJA1105RELY
✅ Drop-In📋 Reference alternative (not in catalog)
SJA1105TELY
✅ Drop-In📋 Reference alternative (not in catalog)
SJA1105SELY Maximum Ratings & Electrical Characteristics
| Function | 5-Port Automotive Ethernet Switch |
| Protocol | IEEE 802.3, AVB, TSN |
| Number of Ports | 5 |
| Host Interface | SPI |
| Port Speed | 10/100/1000 Mbit/s |
| Uplink Interface | SGMII |
| Supply Voltage | 1.65 V to 3.6 V |
| Architecture | Store-and-Forward |
| Security Features | Frame listing, MAC authentication |
| Package | 159-LFBGA (12x12 mm) |
| Mounting Type | Surface Mount |
| Automotive Qualification | AEC-Q100 |
| RoHS Status | Compliant |
SJA1105SELY 159-lfbga (12x12 mm) Pin Configuration Guide
Pin configuration for SJA1105SELY (159-lfbga (12x12 mm) package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for SJA1105SELY.
Refer to the datasheet for full pin configuration.
Typical Applications
SJA1105SELY is suitable for 6 applications: Automotive Zonal Gateway ECU, ADAS Sensor Aggregation Hub, In-Vehicle Infotainment Backbone, Body Controller Domain Network, Industrial TSN Bridge, Service-Oriented Gateway (SDV Architectures).
Automotive Zonal Gateway ECU
The SJA1105SELY's 5 gigabit ports and SGMII uplink make it ideal as the central Ethernet switch in automotive zonal gateway ECUs. Each of the five ports can be assigned to a vehicle zone (front, rear, left, right, cockpit) and backhauled via SGMII to the central compute SoC. The hardware AVB/TSN scheduling ensures deterministic latency for ADAS sensor streams crossing the gateway, and the AEC-Q100 Grade 2 qualification handles -40C to +105C underhood conditions. Pin-compatible with the rest of the SJA1105PEL/QEL/REL/SEL family for PCB reuse across vehicle programs.
Recommended
ADAS Sensor Aggregation Hub
In ADAS sensor aggregation designs the SJA1105SELY consolidates data from multiple camera, radar, and lidar ECUs onto a single gigabit backbone. The integrated 802.1AS hardware timestamping synchronizes sensor timestamps to within microsecond accuracy across the switch fabric, and the 5-port store-and-forward architecture handles aggregate bandwidth up to 5 Gbit/s without head-of-line blocking. The SGMII uplink interfaces directly to ADAS domain SoCs like the NXP S32V234 or third-party NVIDIA/Qualcomm processors. AEC-Q100 qualification is required for underhood or cabin-mounted ECU placement.
Recommended
In-Vehicle Infotainment Backbone
The SJA1105SELY's AVB hardware acceleration enables deterministic transport of uncompressed audio and video streams across the in-vehicle infotainment (IVI) backbone. Multiple head-unit display nodes, rear-seat entertainment modules, and amplifier ECUs connect via 100/1000BASE-T1 links, with the switch performing stream reservation and QoS prioritization per 802.1Qat SRP. The SGMII host port connects to the head-unit SoC without external PHY overhead, saving PCB area and BOM cost. 1.65V-3.6V supply flexibility simplifies the mixed-rail power tree typical in IVI designs.
Recommended
Body Controller Domain Network
Body controller domains (lighting, door modules, HVAC) increasingly migrate from CAN/LIN to 100BASE-T1 Ethernet, and the SJA1105SELY provides a 5-port switch capable of aggregating all body subdomains into a single zonal ECU. The integrated frame-listing security feature prevents unauthorized ECUs from injecting malicious frames, addressing ISO/SAE 21434 cybersecurity requirements. Hardware AVB/TSN scheduling supports deterministic door-mirror camera streams at fixed latency. AEC-Q100 Grade 2 qualification handles the -40C to +105C temperature range of body controller modules mounted behind the dashboard.
Recommended
Industrial TSN Bridge
Outside automotive, the SJA1105SELY serves as a TSN bridge in industrial automation networks where deterministic Ethernet is replacing legacy fieldbus. Five gigabit ports connect motion controllers, vision systems, and safety PLCs, with 802.1Qbv time-aware shaping guaranteeing bounded latency for synchronized motion axes. The SGMII uplink attaches to an industrial edge gateway or PLC backplane. While the SJA1105SELY is AEC-Q100 qualified, industrial designs often prefer the SJA1105TELY variant for cost optimization when automotive qualification is not required. Pin-compatible footprint allows field upgrades.
Recommended
Service-Oriented Gateway (SDV Architectures)
In software-defined vehicle (SDV) architectures, the SJA1105SELY functions as the central Ethernet switch in service-oriented gateways that abstract vehicle signals from physical ECUs. The 5-port gigabit switch fabric handles high-throughput east-west traffic between domain controllers, while the SGMII uplink provides a 1 Gbit/s link to the central compute SoC running AUTOSAR Adaptive or hypervisor-based service orchestration. Hardware timestamping and TSN scheduling preserve time-correlation for sensor-fusion workloads. The wide 1.65V-3.6V supply range simplifies integration into multi-rail SDV power trees.
Recommended
Recommended Products Summary
Engineering reference data for SJA1105SELY — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SJA1105PELY | SJA1105QELY | SJA1105RELY | SJA1105TELY |
|---|---|---|---|---|---|
| Package | 159-LFBGA (12x12 mm) | 159-LFBGA (12x12 mm) - same | 159-LFBGA (12x12 mm) - same | 159-LFBGA (12x12 mm) - same | 159-LFBGA (12x12 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Number of Ports | 5 | 5 | 5 | 5 | 5 |
| Host Interface | SPI (with SGMII uplink) | SPI (RGMII uplink) | SPI (RGMII uplink) | SPI (RGMII uplink) | SPI (RGMII uplink) |
| TSN Support | Yes (full TSN) | No (AVB only) | Yes | Yes (TTEthernet + TSN) | Yes (industrial TSN) |
| Frame Listing Security | Yes | No | Yes | Yes | Yes |
| Automotive Qualification | AEC-Q100 Grade 2 | AEC-Q100 Grade 2 | AEC-Q100 Grade 2 | AEC-Q100 Grade 2 | Industrial (no AEC-Q100) |
| 1 pc Price (USD, approx) | $12.45 | $11.50 | $13.00 | $13.50 | $10.80 |
Key Differentiators
- Integrated SGMII uplink for direct SoC connection (vs SJA1105PELY)
- Full TSN support with frame listing (vs SJA1105PELY)
- AEC-Q100 Grade 2 automotive qualification (vs SJA1105TELY)
Design Notes
The 159-LFBGA package with 0.8 mm pitch requires a 4-layer PCB minimum, with laser-drilled stacked microvias (via-in-pad recommended) for the inner ball rows. Place decoupling capacitors within 2 mm of each supply ball - typical design uses 100 nF X7R plus 4.7 uF bulk per supply rail. The center thermal pad array must be soldered to a continuous ground plane for thermal dissipation. Per NXP's SJA1105 datasheet, signal integrity on the SGMII traces requires 100 ohm differential impedance with length matching within 0.5 mm.
Provide a clean 1.65V-3.6V supply to VDD pins with separate analog and digital rails if the design mixes 1.8V PHYs with 3.3V GPIO. Per NXP's application guidance, isolate the SGMII PLL supply with a ferrite bead and local 10 uF + 100 nF decoupling. Power-on sequencing is not strictly required but reset (NRESET) must be held low for at least 10 ms after all rails reach regulation. Estimated: typical operating power is 1.5-2.0 W at full gigabit load across five ports.
Route SGMII differential pairs with 100 ohm controlled impedance, length-matched within 0.5 mm (per NXP SJA1105 datasheet). Avoid routing SGMII across plane splits; use a continuous ground reference beneath the pair. The SPI host interface runs up to 25 MHz - keep traces short and add 33 ohm series termination at the source if the SPI bus exceeds 50 mm. The MII/RGMII interface to companion PHYs must be length-matched within 1 mm on each byte lane to preserve setup/hold timing.
Common pitfalls include: (1) forgetting to program the SPI host interface for the correct endianness during MCU bootloader init, leaving the switch in an unconfigured state; (2) omitting the external 25 MHz reference oscillator, which the SJA1105 requires for SGMII operation; (3) connecting the SGMII pairs with incorrect polarity (the SELY variant auto-detects but check via the status register); (4) failing to populate the frame-listing whitelist table at boot, which the SELY variant requires for all ports to forward traffic.
Compliance Information
AEC-Q100 Grade 2 qualified for automotive applications. RoHS compliant per NXP product page. Halogen-free status not explicitly stated in provided data.
