TDA235E0 - 300A Dual-Phase Smart Power Stage | Infineon
MPN: TDA235E0 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.5 | $5,250.00 |
| 1,000 | $9.4 | $9,400.00 |
| 3,000 | $8.2 | $24,600.00 |
TDA235E0 Overview
A smart power stage (SPS) is an integrated power-conversion building block that combines the high-side and low-side MOSFETs, gate drivers, current sensing, and protection circuitry into a single package, enabling multi-phase buck regulators that feed low-core voltages (typically 0.6 V to 1.2 V) to high-current processors. Smart power stages sit below multi-phase controllers and DC-DC converter ICs in the power management hierarchy, and are a category of point-of-load (PoL) regulators optimized for AI/GPU/ASIC silicon. They expose per-phase current and temperature telemetry to the upstream controller for adaptive voltage positioning, load-line regulation, and fault management.
Key features of the TDA235E0 include integrated OptiMOS 6 technology for best-in-class figure-of-merit (FOM), a precision per-phase current-sense output for multi-phase current balancing and telemetry, built-in protection (over-current, over-temperature, under-voltage), high switching frequency support for reduced output inductance, and top-side thermal pad optimized for cold-plate liquid cooling. The exposed top side has low junction-to-top-side thermal impedance to facilitate direct-to-cold-plate heat removal in server racks.
The architecture pairs two synchronous buck power stages (each a high-side + low-side OptiMOS 6 half-bridge plus gate driver) inside one package, sharing a common bootstrap and ground reference. Telemetry includes per-phase analog current output and overtemperature flag. Compared with discrete DrMOS implementations, the TDA235E0 reduces PCB footprint, eliminates parasitic loop inductance between MOSFETs and driver, and simplifies multi-phase interleaving for 6-phase or 8-phase VRs feeding 600 A-class GPU/ASIC cores.
Typical applications include AI accelerator core rails (GPU, TPU, custom ASICs at 600-1000 A), server CPU voltage regulators, vertical power delivery modules for processor sockets, high-performance computing motherboards, and 48 V direct-to-load buck stages where two TDA235E0 phases feed a secondary-side multi-phase VR. The compact 6x6 mm footprint allows 8-phase solutions to fit beneath BGA sockets.
When designing with the TDA235E0, follow the manufacturer's recommended PCB layout for input capacitors and gate-drive return paths to minimize switching losses. Ensure the upstream multi-phase controller is compatible with Infineon's SPS interface (current-sense and temperature-flag timing); the TDA235E0 is pin-compatible with the higher-current TDA235E5 variant in the same family.
This page synthesizes Infineon launch information, distributor pricing references, and design considerations not found in a single datasheet, including drop-in alternatives and liquid-cooling thermal guidance.
Drop-in alternatives for TDA235E0 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with TDA235E0 (same form factor and footprint) — differing in Mounting Type, Package, Power Density, Telemetry.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
TDA235E5
✅ Drop-In✓ In Stock
$10.2 / Unit
View Datasheet →TDA235E0
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →TDA235E0
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →TDA235E0 Maximum Ratings & Electrical Characteristics
| Topology | Dual-phase smart power stage (integrated driver + OptiMOS 6 MOSFETs) |
| Peak Current per Phase | 300 A |
| Total Design Current | 120 A |
| Power Density | > 2 A/mm² |
| MOSFET Technology | Infineon OptiMOS 6 |
| Package | 6 x 6 x 0.8 mm³ PQFN-style SMD |
| Mounting Type | Surface Mount, top-side exposed thermal pad |
| Cooling | Liquid cooling compatible (top-side thermal pad for cold-plate) |
| Power Delivery | Lateral and vertical power delivery (VPD) support |
| Telemetry | Per-phase current sense output, temperature flag |
| Protection Features | Over-current, over-temperature, under-voltage |
| Compliance | RoHS compliant (per Infineon product page) |
TDA235E0 6 x 6 x 0.8 mm³ pqfn-style smd Pin Configuration Guide
Pin configuration for TDA235E0 (6 x 6 x 0.8 mm³ pqfn-style smd package). This power device features gate, drain, and source terminals. For non-polarized packages, refer to the manufacturer datasheet for exact pin 1 orientation and footprint details. Common applications include power supply design, motor driving, and load switching.
No detailed pinout data available for TDA235E0.
Refer to the datasheet for full pin configuration.
Typical Applications
TDA235E0 is suitable for 6 applications: AI Accelerator Core Voltage Regulator, Server CPU Voltage Regulator, Vertical Power Delivery (VPD) Module, 48V Direct-to-Load Buck Stage, High-Performance Computing Motherboard, AI Inference Accelerator Card.
AI Accelerator Core Voltage Regulator
The TDA235E0's 300 A peak per-phase current and > 2 A/mm² power density make it ideal for AI accelerator core rails delivering 0.6-1.0 V to GPU, TPU, and custom ASIC processors at 600-1000 A total load. Placed in a 6-phase or 8-phase VR configuration beneath the processor BGA, each TDA235E0 provides telemetry for adaptive voltage positioning and current balancing across phases. The top-side thermal pad interfaces with a cold-plate for liquid cooling in high-density AI training and inference servers.
Recommended
Server CPU Voltage Regulator
In high-core-count server CPUs (Intel Xeon, AMD EPYC) requiring 200-400 A core current, the TDA235E0 enables a compact 4-phase or 6-phase VR solution in standard server form factors. The integrated OptiMOS 6 MOSFETs minimize switching losses at 1-2 MHz operation, while the analog telemetry enables dynamic load-line regulation requested by modern server CPUs. The 6 x 6 mm footprint fits within the VR region beneath the CPU socket with adequate clearance for input capacitor placement.
Recommended
Vertical Power Delivery (VPD) Module
The TDA235E0 supports vertical power delivery modules (VPDMs) where power is delivered vertically from a side-mounted or bottom-mounted VR through the processor substrate to the die. Its dual-phase architecture and integrated current sense allow precise per-phase telemetry across an 8-phase VPDM design. The lateral and vertical power delivery support specified by Infineon enables the TDA235E0 to feed either lateral motherboard VRs or VPDMs in next-generation AI server chassis.
Recommended
48V Direct-to-Load Buck Stage
In 48 V direct-to-load architectures (Open Compute Project 48V spec), the TDA235E0 serves as a secondary-side multi-phase buck stage fed by a primary 48V-to-intermediate-bus converter. Each TDA235E0 phase delivers up to 300 A peak to the load at low voltage (0.6-1.2 V), eliminating the intermediate bus and reducing distribution losses. The dual-phase integration reduces per-phase PCB footprint by 50% compared with discrete DrMOS implementations in equivalent 48V-to-load designs.
Recommended
High-Performance Computing Motherboard
For HPC motherboards powering FPGAs (Xilinx Versal, Intel Agilex) and high-bandwidth memory at 100-300 A currents, the TDA235E0's small 6 x 6 mm footprint and integrated driver minimize motherboard layer count. The exposed top-side thermal pad interfaces with chassis air-cooled heat sinks in HPC workstations or cold plates in liquid-cooled HPC racks. Built-in OCP/OTP/UVLO protection provides per-phase fault isolation without external supervisor circuitry.
Recommended
AI Inference Accelerator Card
Edge and data-center AI inference accelerators (NVIDIA L4, Intel Gaudi, custom NPU ASICs) at 200-500 A total current benefit from the TDA235E0's compact multi-phase VR implementation. A 2-phase or 4-phase TDA235E0 design fits within the accelerator card's power envelope while delivering precise load-line regulation and per-phase current telemetry for predictive maintenance. The Infineon OptiMOS 6 technology reduces total harmonic distortion (THD) and improves efficiency under AI inference load transients.
Recommended
Recommended Products Summary
Engineering reference data for TDA235E0 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TDA235E5 |
|---|---|---|
| Package | 6 x 6 x 0.8 mm³ PQFN | 6 x 6 x 0.8 mm³ PQFN - same |
| Brand | Infineon | Infineon - same |
| Topology | Dual-phase smart power stage | Dual-phase smart power stage - same |
| Peak Current per Phase | 300 A | >300 A (higher-current sibling) |
| Total Design Current | 120 A | Higher than 120 A |
| Power Density | > 2 A/mm² | > 2 A/mm² - same family benchmark |
| MOSFET Technology | OptiMOS 6 | OptiMOS 6 - same |
| Liquid Cooling Support | Yes (top-side exposed thermal pad) | Yes (same package top-side pad) |
Key Differentiators
- Higher power density than most competing 6x6 mm smart power stages (vs TDA235E5)
- Integrated OptiMOS 6 MOSFETs in dual-phase configuration (vs Discrete DrMOS implementations)
- Top-side exposed thermal pad optimized for liquid cooling (vs Standard bottom-cooled PQFN smart power stages)
Design Notes
The TDA235E0 is designed for direct cold-plate liquid cooling via its top-side exposed thermal pad. Per Infineon's launch announcement, the device has low junction-to-top-side thermal impedance optimized for cold-plate mounting in AI server racks. Designers should specify a thermal interface material (TIM) with conductivity > 5 W/mK between the TDA235E0 top-side pad and the cold plate, and ensure the cold-plate surface flatness is < 0.05 mm to maintain uniform contact pressure across all phases in a multi-phase VR.
Place input bulk capacitors as close as possible to the TDA235E0 high-side MOSFET drain pads to minimize switching loop inductance, following Infineon's recommended layout in the datasheet. Use a 4-layer PCB minimum with continuous ground and power planes beneath the device; allocate at least 2 oz copper on outer layers for high-current phase output paths. Keep the analog current-sense and temperature-flag traces away from switching nodes and route them as differential pairs with ground shielding to preserve telemetry accuracy.
Do not assume the TDA235E0 is pin-compatible with earlier discrete DrMOS or DrMOS-derived smart power stage designs from other vendors (MPS, ON Semi, Renesas) without verifying pinout against the manufacturer's footprint reference. Although the 6 x 6 mm PQFN outline is widely adopted, the pin assignments for current-sense, bootstrap, and fault-flag differ between vendors. Always cross-check the Infineon footprint symbol against the target PCB footprint before PCB fabrication to avoid costly board respins.
Compliance Information
RoHS and REACH compliance per Infineon product page. Not AEC-Q100 qualified (this is a server/AI accelerator product, not automotive).
