XRD87L75AID-F - 8-Bit 10MSPS ADC | 20-SOIC | MaxLinear
MPN: XRD87L75AID-F ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.78 | $57.80 |
| 100 | $5.1 | $510.00 |
| 500 | $4.32 | $2,160.00 |
| 1,000 | $3.79 | $3,790.00 |
XRD87L75AID-F Overview
An 8-bit flash ADC is a type of analog-to-digital converter that uses a parallel bank of 2^n comparators to convert an input voltage into a digital code in a single clock cycle, achieving the fastest possible conversion latency at moderate resolution. Within the broader signal-chain taxonomy, the XRD87L75AID-F sits between a traditional sample-and-hold stage and a digital host (FPGA, ASIC, or microcontroller), and is a member of the speed-optimized, low-resolution ADC family used for video, instrumentation, and IF digitisation.
Key features include 8-bit resolution, a 10 MHz typical sampling rate, an internal track-and-hold, an analog input range of 0V to VDD, a reference input range of 1V to VDD, and typical power dissipation of 25 mW (excluding reference current). The device is latch-up free, operates from a single 3.3V supply, and uses a parallel CMOS-compatible digital interface, which simplifies connection to modern MCUs and FPGAs without external level shifters.
The device is built on an advanced 3.3V CMOS process and uses a flash architecture to deliver 10 MSPS conversion speeds. Its internal S/H function guarantees a stable sample window across rapidly-changing inputs and avoids the need for external S/H circuitry, simplifying the analog front-end.
Typical applications include video digitisation, CCD imaging front-ends, digital oscilloscope front-ends, IF sampling in communications, portable instrumentation, and general-purpose high-speed data acquisition. The wide analog input range (0V to VDD) lets designers digitise single-ended signals without external attenuators.
When designing with this device, ensure the analog input is properly driven (low-impedance buffer recommended) and that the reference decoupling is solid. The single 3.3V supply simplifies the power tree but requires that downstream digital logic be 3.3V tolerant.
This page synthesises distributor pricing, drop-in alternatives (including the SSOP-packaged variant XRD87L75AIU-F), and practical design notes that complement the manufacturer datasheet.
Drop-in alternatives for XRD87L75AID-F — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with XRD87L75AID-F (same form factor and footprint) — differing in Architecture, Resolution, Mounting Type, Number of Channels, Latch-Up.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
XRD87L75AIU-F
✅ Drop-In📋 Reference alternative (not in catalog)
MAX1180
✅ Drop-In📋 Reference alternative (not in catalog)
TLV2545IDGKRG4
✅ Drop-In✓ In Stock
$3.1 / Unit
View Datasheet →MAX1285BCSA+
✅ Drop-In📋 Reference alternative (not in catalog)
XRD87L75AID-F Maximum Ratings & Electrical Characteristics
| Resolution | 8 bits |
| Sampling Rate | 10 MSPS (max) |
| Number of Channels | 1 |
| Architecture | Flash ADC with internal S/H |
| Analog Input Range (VIN DC) | 0 V to VDD |
| Reference Input Range (VREF DC) | 1 V to VDD |
| Supply Voltage | 3.3 V (single supply) |
| Power Dissipation (typ, excluding reference) | 25 mW |
| Data Interface | Parallel (CMOS-compatible) |
| Operating Temperature Range | -40 °C to +85 °C |
| Package / Case | 20-SOIC (0.295" / 7.50 mm body width) |
| Mounting Type | Surface Mount |
| Packaging | Tube (-F factory suffix) |
| Latch-Up | Latch-up free |
XRD87L75AID-F Pin Configuration
| Pin 1 | [DATA_NEEDED: pin 1 name] — [DATA_NEEDED: pin 1 function - refer to datasheet pinout] |
| Pin 2 | [DATA_NEEDED: pin 2 name] — [DATA_NEEDED] |
| Pin 3 | [DATA_NEEDED: pin 3 name] — [DATA_NEEDED] |
| Pin 4 | [DATA_NEEDED: pin 4 name] — [DATA_NEEDED] |
| Pin 5 | [DATA_NEEDED: pin 5 name] — [DATA_NEEDED] |
| Pin 6 | [DATA_NEEDED: pin 6 name] — [DATA_NEEDED] |
| Pin 7 | [DATA_NEEDED: pin 7 name] — [DATA_NEEDED] |
| Pin 8 | [DATA_NEEDED: pin 8 name] — [DATA_NEEDED] |
| Pin 9 | [DATA_NEEDED: pin 9 name] — [DATA_NEEDED] |
| Pin 10 | [DATA_NEEDED: pin 10 name] — [DATA_NEEDED] |
| Pin 11 | [DATA_NEEDED: pin 11 name] — [DATA_NEEDED] |
| Pin 12 | [DATA_NEEDED: pin 12 name] — [DATA_NEEDED] |
| Pin 13 | [DATA_NEEDED: pin 13 name] — [DATA_NEEDED] |
| Pin 14 | [DATA_NEEDED: pin 14 name] — [DATA_NEEDED] |
| Pin 15 | [DATA_NEEDED: pin 15 name] — [DATA_NEEDED] |
| Pin 16 | [DATA_NEEDED: pin 16 name] — [DATA_NEEDED] |
| Pin 17 | [DATA_NEEDED: pin 17 name] — [DATA_NEEDED] |
| Pin 18 | [DATA_NEEDED: pin 18 name] — [DATA_NEEDED] |
| Pin 19 | [DATA_NEEDED: pin 19 name] — [DATA_NEEDED] |
| Pin 20 | [DATA_NEEDED: pin 20 name] — [DATA_NEEDED] |
Typical Applications
XRD87L75AID-F is suitable for 6 applications: Video Digitisation Front-End, CCD Imaging Data Acquisition, IF / Communications Sampling, Portable Instrumentation, Industrial Control Digitisation, Ultrasound / Medical Imaging Front-End.
Video Digitisation Front-End
The XRD87L75AID-F's 10 MSPS flash architecture and 0V-VDD analog input window are well-matched to standard-definition and pixel-rate video digitisation. The internal sample-and-hold maintains stable conversion of high-frequency pixel transitions without external S/H, while the 3.3V CMOS parallel interface connects directly to video ASICs and FPGAs. Designers use the part at sub-Nyquist rates for sub-pixel sampling. Trade-off vs 27 MHz video standards: pipeline/dual-channel devices are required for full BT.601 compliance.
Recommended
CCD Imaging Data Acquisition
CCD output stages require digitisation at pixel clock rates with low-latency parallel conversion. The XRD87L75AID-F's 8-bit flash topology adds only one clock of pipeline delay, simplifying frame buffer alignment, while its single 3.3V supply reduces the analog front-end's bill of materials. The wide analog input (0V to VDD) accepts direct CCD coupling when the signal swing is below 3.3V. Trade-off: limited 8-bit dynamic range vs 10/12-bit CCD competitors.
Recommended
IF / Communications Sampling
Intermediate-frequency sampling at baseband-to-low-IF requires an ADC that can run at 10 MSPS without pipeline latency. The XRD87L75AID-F's flash topology delivers single-cycle conversions, and the parallel CMOS interface feeds downstream DSP/FPGA I/O directly. Its 3.3V supply matches modern baseband ASIC rails. Trade-off: 8-bit resolution caps dynamic range at complex modulation schemes; suitable for OOK/FSK sub-systems and pilot-channel sampling rather than wideband QAM.
Recommended
Portable Instrumentation
Battery-powered test and measurement gear benefits from the XRD87L75AID-F's 25 mW typical power budget and single 3.3V supply. The wide input range accepts direct sensor coupling, and the parallel interface avoids the overhead of an SPI/QSPI controller. Plastic 20-SOIC packaging supports compact PCB layouts typical of handheld DMMs and oscilloscope probes. Trade-off: only 8-bit precision, so not appropriate for precision lab meters.
Recommended
Industrial Control Digitisation
Industrial sensors, encoders, and vibration monitors often need 10 MSPS-class conversion to capture transients. The XRD87L75AID-F's -40 to +85 °C industrial temperature range and 3.3V CMOS logic suit PLC backplanes and motor-control cards. The internal S/H simplifies burst-mode acquisition of mechanical events. Trade-off: parallel interface requires more host pins than serial-output ADCs and may demand bus multiplexing on dense boards.
Recommended
Ultrasound / Medical Imaging Front-End
Low-cost ultrasound front-ends use 8-10 MSPS ADCs in the beamformer path. The XRD87L75AID-F's flash architecture adds only one clock delay, ideal for phasing and beam-steering math, and the wide analog input window accepts DC-coupled transducer outputs. The latch-up free CMOS process provides the reliability expected in medical electronics when paired with appropriate isolation. Trade-off: limited 8-bit resolution constrains dynamic range; high-end ultrasound systems need 12+ bit pipelines.
Recommended
Recommended Products Summary
Engineering reference data for XRD87L75AID-F — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XRD87L75AIU-F | MAX1180 | TLV2545IDGKRG4 | MAX1285BCSA+ |
|---|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | Analog Devices | Texas Instruments | Analog Devices |
| Package | 20-SOIC (D suffix, 0.295") | 20-SOIC (functionally similar) | 20-SOIC (functional only) | 20-SOIC (functional only) | 20-SOIC (functional only) |
| Resolution | 8 bits | 8 bits | 10 bits | 12 bits | 12 bits |
| Sampling Rate | 10 MSPS | 10 MSPS | 105 MSPS | 200 kSPS | 300 kSPS |
| Supply Voltage | 3.3 V single | 3.3 V single | 2.7-5.25 V single | 2.7-5.5 V single | 2.7-3.6 V single |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | SPI/QSPI/µWire | SPI |
| Internal S/H | Yes | Yes | Yes | Yes (SAR input stage) | Yes |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | 0 °C to +70 °C |
Key Differentiators
- Flash architecture = single-cycle conversion (vs TLV2545IDGKRG4 (SAR))
- Higher speed at the same resolution (vs MAX1285BCSA+ (12-bit 300 kSPS))
- Narrower/denser pin-compatibility universe (vs MAX1180 (10-bit 105 MSPS))
Design Notes
Place the analog input (VIN) trace as short as possible and route it over a continuous ground plane to minimise coupled noise. A single-pole RC anti-alias filter at 4-5 MHz should be placed near the VIN pin to band-limit wideband noise before the internal S/H samples; recommended source impedance is below 1 kohm to avoid THD degradation. The VREF pin must be decoupled with a 100 nF ceramic plus 10 µF tantalum bypass directly at the pin.
The XRD87L75AID-F runs from a single 3.3V supply; star-route the analog VDD to a ferrite bead from the digital 3.3V rail to keep digital switching transients out of the analog front-end. Decouple VDD with both a 100 nF ceramic and a 10 µF tantalum at each pin pair. The reference pin (VREF) should be driven from a low-noise reference such as an ADR01 or REF3133 rather than from a resistor divider to maintain full 8-bit linearity.
Avoid driving VIN with signals exceeding VDD + 0.3 V - the input protection diodes will conduct and distort the sample. The clock source must be clean (jitter < 50 ps rms) because flash-ADC aperture is small and clock jitter directly converts to conversion noise. Do not leave the digital outputs floating during conversion - this can inject coupling noise back into VIN via the substrate; tie any unused outputs to GND or a defined logic level.
The 8-bit parallel bus can switch simultaneously at 10 MSPS, generating sub-nanosecond edge rates. Route the digital output bus as a tight, impedance-matched group (typically 50 ohm to GND) with a small damping resistor (22-33 ohm) in series near the driver to limit overshoot. Keep the bus at least 3 trace widths from any analog signal path to maintain target SINAD.
Compliance Information
Compliance status not explicitly stated in the provided MaxLinear/Exar datasheet excerpt; verify RoHS/REACH on the manufacturer product page before placing volume orders.
