Near-memory computing moves toward AI inference workloads

Reported by Semiconductor Engineering on November 12, 2026. Summarized and analyzed by XAIPART Editorial.

What happened

Edge AI inference is encouraging chip and system designers to place more computation near memory, reducing transfers between processors and data stores while addressing tight power limits.^S1 Candidate approaches include processing near memory, called PNM, processing in memory, called PIM, and compute-in-memory architectures that perform calculations within a memory array.^S1 Processing in the same package through custom HBM or on the same die through LPDDR6-PIM can shorten data paths and improve performance.^S1

The article distinguishes hardware compute-in-memory from the separate enterprise-software meaning of IMC, which runs databases and analytics from RAM rather than disk.^S1 In hardware, analog multiply-accumulate operations can execute on SRAM or ReRAM bitlines, while digital PIM places logic beside DRAM banks.^S1 PNM instead places logic on a separate die within the memory package, including proposed custom HBM4 and HBM4E base dies.^S1 Expedera cautioned that near-memory designs work well for low-batch decode, but large-batch decode and prefill make activation communication more difficult.^S1

Adoption remains constrained by software, manufacturing, cost, and thermal issues.^S1 Compilers, operating systems, memory controllers, and processors need protocols and scheduling support for offloaded operations, while combining logic and DRAM processes can increase manufacturing expense.^S1 Samsung has published the architecture and performance benchmarks for an LPDDR6-PIM chip targeting low-power mobile on-device AI, and JEDEC work on the standard is nearing completion.^S1 Thermal design is also critical because stacking memory near logic concentrates heat and can create thermo-mechanical stress.^S1

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.