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EPC1PI8 - Altera 1Mb OTP Serial Config PROM | 8-PDIP
The Altera EPC1PI8 is a 1-Mbit one-time-programmable (OTP) serial configuration PROM designed to store FPGA configuration bitstreams for Altera/Intel SRAM-based LUT devices such as ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX. The device operates at up to 8 MHz configuration clock frequency, supports 5 V (4.5 V – 5.5 V) and 3.3 V (3.0 V – 3.6 V) supplies, and ships in an 8-pin PDIP through-hole package. Background: A configuration PROM is a non-volatile serial memory that holds the FPGA's bitstream so that an SRAM-based FPGA can be reconfigured at every power-up. The hierarchy is: configuration PROM -> serial configuration memory -> non-volatile memory -> programmable logic support IC. Unlike SPI flash or parallel boot PROMs, configuration PROMs use a dedicated FPGA configuration protocol (FPP, PS, or AS modes) and are optimized for short bitstreams with deterministic configuration time. EPC1-series PROMs are typically paired with older Altera FPGAs that pre-date modern EPCQ/QSPI flash boot solutions. Key features include 1 Mb of OTP storage, 8 MHz maximum DCLK frequency, a simple 4-wire serial interface (nCS, DCLK, DATA, OE), and dedicated FPGA-configuration timing. The device is one-time-programmable (not erasable), which suits production systems where the bitstream is finalized. EPC1PI8 supports both 3.3 V and 5 V VCC operation, allowing direct interface to 5 V-tolerant FPGA configuration pins. The EPC1 architecture uses a serial shift-register programming model with internal charge-pump generated programming voltages. Configuration data is clocked out LSB-first, MSB-first on a per-Altera-FPGA basis, and OE/nCS provide frame-level handshaking. Because the part is OTP, no UV window or in-system erase is possible - it is intended as the lowest-cost permanent configuration storage. Typical applications include legacy Altera/Intel FPGA configuration in industrial controllers, prototyping boards for Cyclone and APEX families, low-volume production systems, and as a second-source PROM in designs migrating from discontinued configuration devices. It is widely used on Altera/Intel development kits to demonstrate the configuration chain. When designing with EPC1PI8, observe the VCC ramp time and follow the Altera FPGA configuration handshake sequence exactly. Because EPC1PI8 is OTP, plan for a small number of pre-programmed parts during development; sample/engineering units should be ordered with known-good bitstreams. This page synthesizes distributor availability, lifecycle status, drop-in EPC1/EPC2 alternatives from the same Altera family, and practical design considerations not found in the original datasheet.
EPC1PI8N - 1Mb OTP FPGA Config PROM, 8-PDIP | Altera / Intel
The Altera / Intel EPC1PI8N is a 1-Mbit one-time programmable (OTP) configuration PROM designed to store configuration bitstreams for Altera SRAM-based LUT FPGAs, housed in an 8-pin PDIP through-hole package. It supports dual supply operation at 3.0V-3.6V or 4.5V-5.5V and delivers factory-programmed configuration to FPGAs in the ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K and Mercury families via a simple serial interface. What is an FPGA configuration PROM? An FPGA configuration PROM is a non-volatile memory that holds the FPGA's bitstream and loads it into the SRAM-based logic fabric at power-up. PROMs sit in the boot chain between a board-level storage source and the FPGA, occupying the same category as boot EEPROMs and flash-loader devices. As a member of the broader FPGA configuration memory family, it bridges firmware storage and volatile programmable logic, and is itself a sub-class of non-volatile serial memory in the memory IC hierarchy. Key differentiating features include 1-Mbit density, an industry-standard 4-pin serial interface (DATA, DCLK, nCS, OE), low-power CMOS technology and an operating temperature range of -40C to +85C. The 'N' suffix designates the standard 8-PDIP 0.300 inch through-hole package, and the 'I' indicates the industrial temperature grade. The EPC1PI8N is built on a CMOS OTP process, allowing one-time in-system or pre-programmed configuration. Programming is performed by Altera's Quartus / MAX+PLUS II toolchain with the Altera Programming Unit (APU) or third-party programmers that support the EPC1 instruction set. Typical applications include low-volume FPGA designs, factory-programmed industrial controllers, prototyping boards for legacy Altera FPGAs, and cost-sensitive embedded platforms that prefer a discrete configuration memory over a parallel flash plus controller. Its dual-voltage supply range allows direct interfacing to both 3.3V and 5V FPGA banks. Design trade-off: because the EPC1PI8N is OTP, any firmware update requires a physical device swap or socketed adapter. Designers who anticipate in-field firmware revision should consider JTAG-direct configuration, a flash-based equivalent, or a socketed DIP footprint.
EPC1TI32 - Altera 1Mb Config PROM, 32-TQFP | Intel FPGA Loader
The Altera (now Intel) EPC1TI32 is a 1-Mbit serial configuration PROM designed to load the configuration bitstream into Altera FPGAs such as the ACEX 1K, FLEX 10K, FLEX 6000, and MAX 9000 families. Housed in a 32-pin Thin Quad Flat Pack (TQFP) package, the device provides a compact, board-level non-volatile storage solution for FPGA configuration data and is programmed in-system via the JTAG interface or with a standard Altera programming hardware. A configuration PROM is a non-volatile memory device whose sole purpose is to store the configuration bitstream of an FPGA or CPLD at power-up. In the broader system taxonomy it sits under FPGA configuration memory -> serial PROM -> non-volatile memory -> semiconductor memory. The EPC1 sits at the entry level of Altera's enhanced configuration family (EPC1 / EPC2 / EPC4 / EPC8 / EPC16), each step doubling memory density to address progressively larger FPGA bitstreams. Key features include 1,046,496 bits (1 Mb) of one-time-programmable storage, a simple 4-pin serial interface to the FPGA (nSTATUS, nCONFIG, DCLK, DATA), and 3.3 V or 5 V operation derived from the FPGA's VCCIO supply rail. The device replaces the older EPC1064 and EPC1441 PROMs and is software-compatible with the Altera Quartus and MAX+PLUS II configuration flows. Programming is performed through the JTAG chain (IEEE 1149.1) using a MasterBlaster, ByteBlasterMV, or USB-Blaster download cable. Architecturally the EPC1 uses a single 4-pin synchronous serial protocol where the FPGA generates DCLK and reads DATA on every rising edge. Internally, the memory is organized as a long shift register with an internal oscillator and address counter; no external memory controller is required. A built-in pull-up on nSTATUS and open-drain drivers ease board design when multiple FPGAs share the same JTAG chain. Typical applications include standalone FPGA configuration for industrial controllers, test and measurement front-ends, telecom line cards, and any board where an Altera/Intel FPGA requires local boot memory without an external flash. It is also useful as a low-cost configuration backup when the FPGA's own bitstream needs to be field-upgradable. When designing with the EPC1TI32, route DCLK and DATA as a tightly coupled 50 ohm microstrip pair and place the PROM within 25 mm of the FPGA's configuration pins to avoid signal-integrity issues. The 32-TQFP exposed pad must be soldered to a thermal/ground copper pour to provide mechanical robustness. This page synthesizes distributor availability, drop-in alternative PROMs, and practical board-layout notes beyond the original Altera datasheet, giving engineers a one-stop reference for EPC1TI32 sourcing and replacement decisions.
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
The Altera EPC2-TC32 is an in-system programmable (ISP) configuration PROM designed to load configuration bitstreams into Altera SRAM-based FPGAs, providing 1.6 Mb of non-volatile storage in a 32-pin TQFP (7x7 mm) package. It supports the Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, and FLEX 10K device families via a serial data interface clocked by the FPGA DCLK pin. A configuration PROM is a non-volatile serial memory device that stores the FPGA bitstream and serially shifts it into the target FPGA at power-up through the DATA0/DATA pin, gated by the nCS and OE control signals. The EPC2 sits within the broader hierarchy of FPGA configuration devices, alongside the smaller EPC1 and EPC1441 (older parallel-LUT-era devices) and the larger EPC4/EPC8/EPC16 (enhanced multi-device configuration), as well as the EPCS1/EPCS4/EPCS16/EPCS64 serial flash family introduced for Stratix II and Cyclone families. Key features include 1.6 Mb storage capacity (sufficient for all ACEX 1K, FLEX 10K, APEX 20K, and smaller Cyclone configurations), in-system programmability via the IEEE 1149.1 JTAG interface, an internal oscillator that generates the address counter clocks, and tri-state DATA output buffer controlled by OE and nCS. The device operates from a single 3.3 V supply and offers commercial-grade 0C to +70C temperature range. The EPC2 architecture is built around an EPROM array with an internal address counter and serial output shift register. The internal oscillator eliminates the need for an external configuration clock source in simple single-FPGA designs, while multi-device daisy-chain configurations rely on the FPGA-supplied DCLK to cascade additional EPC2 devices for larger bitstreams. Typical applications include single-FPGA boot configuration for industrial controllers, prototyping boards, and legacy Altera FPGA designs. The JTAG ISP capability allows in-field firmware updates without removing the device from the board, enabling efficient manufacturing flows and field-revision management for deployed systems. When designing with the EPC2-TC32, ensure the JTAG chain shares TDI/TDO/TMS/TCK with the target FPGA so ISP updates do not require board-level rework. The DATA pin must be routed with characteristic impedance matching to the FPGA DATA0 input to prevent signal-integrity issues on the configuration clock edge. This page synthesizes distributor stock, same-family and cross-family drop-in alternatives, and practical design notes not consolidated in the Altera datasheet.
EPC2-TI32 - 1.6Mb In-System Prog Config PROM | Altera | TQFP-32
The Altera EPC2-TI32 is an in-system programmable configuration PROM for SRAM-based FPGAs, providing 1.6 Mbit of non-volatile storage in a 32-pin TQFP (7x7 mm) package. According to the Altera datasheet, the device supports a 10 MHz serial configuration interface and operates from a 3.3V supply, delivering single-device configuration for Altera ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, and other LUT-based FPGA families. A configuration PROM is a non-volatile memory device used to load the bitstream of an SRAM-based FPGA at power-up. Because SRAM cells lose their configuration when power is removed, every SRAM-based FPGA requires an external boot memory. The EPC2 family occupies the configuration-memory tier of the FPGA ecosystem: configuration PROM -> boot memory -> non-volatile memory -> semiconductor. Compared with EPCS serial flash devices, EPC2 offers 5V-tolerant I/O and a wider feature set including in-system programmability via JTAG, multi-device daisy-chain support, and dedicated configuration control pins. Key features include 1.6 Mbit density, in-system programmability through the JTAG interface, 5V tolerant I/O, and open-drain CONF_DONE / nSTATUS pins for multi-FPGA coordination. The device supports daisy-chaining of multiple EPC2 chips to configure larger FPGAs requiring wider bitstreams. The TQFP-32 (7x7 mm) package provides a low-profile surface-mount footprint compatible with standard SMT assembly processes. The EPC2 architecture centers on a reprogrammable CMOS flash array with built-in JTAG controller and Altera-specific serial configuration engine. The internal state machine manages bitstream delivery, error checking, and reconfiguration requests without external intervention. The 5V tolerant I/O simplifies interfacing with mixed-voltage logic in legacy and industrial designs. Typical applications include FPGA configuration for Altera Cyclone, Cyclone II, ACEX 1K, and APEX 20K reference designs, industrial control systems, prototyping platforms, and embedded vision pipelines. The wide FPGA compatibility makes EPC2-TI32 a flexible stock part for designers maintaining legacy Altera designs. When designing with the EPC2-TI32, ensure the JTAG chain is correctly terminated and the nCONFIG / nSTATUS handshaking is properly observed to avoid configuration failure. Designers migrating to newer Altera/Intel FPGA families should evaluate EPCS or EPCQ serial flash devices for lower cost and smaller footprint. This page synthesizes distributor pricing, drop-in TQFP-32 alternatives from the EPC1 and EPC1441 families, and practical design notes for legacy SRAM-based FPGA configuration that are not consolidated in the manufacturer datasheet.
EPC2-TI32N - 1.6Mb In-System Prog Config PROM 32-TQFP | Intel
The Intel EPC2-TI32N is a 1.6Mb in-system programmable configuration PROM designed for use with SRAM-based look-up table (LUT) FPGAs. The device supports dual voltage supply operation (3.0 V to 3.6 V and 4.5 V to 5.5 V) and is housed in a 32-pin TQFP (7 mm x 7 mm) surface-mount package. It is part of the Altera EPC2 family, now manufactured and supported by Intel following the 2015 acquisition of Altera. A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and loads it into the SRAM configuration cells of an SRAM-based FPGA on every power-up. Without a configuration PROM, an SRAM-based LUT FPGA forgets its logic configuration the instant power is removed, because SRAM cells are volatile. The EPC2 family therefore plays a critical role in the FPGA hardware hierarchy, bridging the permanent storage domain (Flash/EEPROM cells inside the EPC2) and the volatile logic domain (FPGA LUT and routing SRAM). Hypernymically, this places the part in the chain: configuration PROM -> serial configuration memory -> non-volatile memory -> memory IC -> integrated circuit. Key features include 1.6 Mb of Flash memory organized as 1,695,680 x 1, an IEEE 1532-compliant JTAG interface for in-system programming, a multi-voltage I/O architecture that interfaces directly to 1.8 V, 2.5 V, 3.3 V and 5 V FPGAs, and a dedicated serial configuration clock output. The 32-TQFP (7x7) package provides a compact 0.8 mm terminal pitch suitable for space-constrained designs and supports an industrial operating temperature range of -40 C to +85 C. Typical applications include storing the configuration bitstream of Altera Cyclone, Cyclone II, Stratix, Stratix II, APEX and other SRAM-based LUT FPGAs in industrial controllers, factory automation equipment, telecommunications line cards, test and measurement instruments, and any system that requires a single-chip, in-system-reprogrammable boot source for an SRAM FPGA. The JTAG ISP capability allows field firmware upgrades without removing the PROM from the board. When designing with this part, note that the EPC2 family is now in the long-term support phase. Designers of new products should evaluate Intel MAX series configuration devices or the latest MAX V/MAX 10 CPLDs with on-chip Flash configuration memory. For legacy board revs, the EPC2-TI32N remains a valid drop-in choice because it shares the same TQFP-32 footprint as the EPC1 and EPC1441 families. This page synthesizes distributor pricing, drop-in pin-compatible alternatives (both same-brand EPC2/EPC1441 variants and cross-brand notes), and practical design considerations not consolidated in the manufacturer datasheet.
EPC20LC20U - PLCC20 Configuration Device | Altera / Intel FPGA
The Altera (now Intel) EPC20LC20U is a 20-pin PLCC configuration device designed to configure SRAM-based Look-Up Table (LUT) FPGAs such as the Altera FLEX 6000/8000 and early Cyclone device families. It belongs to the EPC configuration family (EPC1, EPC2, EPC4, EPC8, EPC16, EPC1441, etc.) that stores the FPGA bitstream in non-volatile memory and streams it to the target device at power-up through a serial configuration interface. EPC20LC20U is delivered in a PLCC-20 (J-lead) through-hole-compatible surface-mount package suitable for legacy and industrial designs where PLCC sockets are still in use. A configuration device is a serial-configuration-memory IC that retains the FPGA's configuration bitstream even when the host system is powered down. On power-up, the FPGA's configuration controller reads the bitstream from the EPC over a serial DATA/DCLK chain, eliminating the need for an external boot PROM in many designs. The EPC family sits in the hierarchy: configuration memory -> non-volatile memory -> memory IC -> semiconductor, and is functionally equivalent to a serial PROM dedicated to FPGA configuration protocols. Key characteristics of EPC20LC20U include a 5.0V tolerant operating supply (per the original Altera EPC2 datasheet that defines the family), a serial configuration interface (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE pins), and compatibility with Altera's proprietary serial configuration protocol. The PLCC-20 (J-lead) package provides mechanical robustness for industrial temperature ranges. In-system programming is supported via Altera's Quartus programmer and the JTAG-style chain, which simplifies board-level bring-up and field firmware updates. Typical applications include configuring Altera FLEX 10K, FLEX 8000, FLEX 6000, APEX, ACEX, and early Cyclone FPGAs in industrial controllers, telecommunications line cards, military/aerospace retrofits, and legacy prototyping platforms. The 20-pin PLCC package is also convenient for socketed debug environments where the configuration bitstream must be swapped frequently during development. When designing with EPC20LC20U, verify that the target FPGA's configuration mode supports the EPC serial protocol and that the JTAG chain ordering matches the Quartus programmer's expected device index. Note that newer Intel/Altera FPGAs use Active Serial (AS) configuration with EPCQ devices instead of EPC devices; EPC20LC20U is intended for legacy FPGA families only. This page synthesizes distributor availability, drop-in alternatives from the same Altera/Intel EPC configuration family, and practical design notes for legacy FPGA configuration that are not found in any single manufacturer datasheet.
EPC21C20U - Altera Configuration Device for SRAM LUT FPGAs
The Altera/Intel EPC21C20U is a 20-Mbit Flash-configuration memory device designed for SRAM-based look-up table (LUT) FPGA families including APEX II, APEX 20KE, APEX 20KC, Mercury, Stratix, Cyclone, ACEX 1K, and FLEX 10KE. Housed in a 20-pin UBGA package (also known as Ultra FineLine BGA), the EPC21C20U stores the configuration bitstream that programs the FPGA at every power-up via the passive or active serial configuration interface. A Configuration Device is a non-volatile serial flash memory that is paired with a volatile SRAM-based FPGA. Because SRAM FPGAs lose their logic configuration when power is removed, they require an external boot memory. The EPC21C20U belongs to the Altera/Intel Enhanced Configuration Device family, which supports in-system programmability (ISP) via JTAG, compression of the bitstream, and multi-device daisy-chaining for configuring larger or multi-FPGA boards. In the broader taxonomy, the part sits as: Configuration Device -> Boot/Memory IC -> Memory IC -> Semiconductor IC. Key features of the EPC21C20U include 20 Mbit (2.5 Mbyte) of storage, in-system programmability through IEEE 1149.1 (JTAG), 3.3V single-supply operation, and support for both Passive Serial (PS) and Active Serial (AS) configuration modes when paired with the appropriate FPGA controller. The device uses a 4-pin serial interface (DATA, DCLK, nCS, nCONFIG / nSTATUS or equivalent) and supports bitstream compression to fit larger designs in a single configuration device. A 2.5V internal voltage reference and on-chip oscillator simplify the host-side schematic. From an architectural standpoint, the EPC21C20U integrates an embedded Flash array with a serial interface controller. Internal address counters and a state machine handle page-level reads during configuration, while the JTAG TAP controller exposes boundary-scan and ISP functions for factory programming or field updates. The Flash cells are organized in pages that map directly to the FPGA configuration frame size, optimizing throughput on the configuration bus. Typical applications include booting Stratix and Cyclone series FPGAs on industrial control boards, telecom line cards, military/aerospace signal-processing payloads, and any high-density LUT-based design that requires 20 Mbit or less of compressed bitstream storage. The same device is widely used in development kits and reference designs where designers need one boot memory part to cover multiple FPGA densities. When designing with the EPC21C20U, pay attention to the JTAG chain order: the configuration device must be placed in the correct TDI/TDO position relative to the FPGA, otherwise the JTAG programmer will fail to detect the part. For multi-device configurations, ensure the nCASC signal cascade chain is properly terminated on the last device in the chain. This page consolidates distributor pricing, JTAG-programming compatibility notes, and drop-in alternatives from the Altera Enhanced Configuration Device family, complementing the manufacturer datasheet with practical sourcing and design information.
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
The Altera (Intel) EPC21LC20 is a 2-Mbit in-system programmable configuration memory device designed to load configuration bitstreams into SRAM-based Altera FPGA and CPLD devices, including ACEX, APEX, Cyclone, FLEX, Mercury, Stratix and similar LUT-based architectures. According to the manufacturer datasheet, the EPC21LC20 supports serial configuration data rates up to 10 MHz in the FPP/PS mode used by these Altera families, with configuration data clocked into the target device on each rising edge of DCLK. The part is supplied in a 20-pin Plastic Leaded Chip Carrier (PLCC-20) package, offered in commercial and industrial operating temperature grades. A configuration PROM is a non-volatile serial memory used at board power-up to load an FPGA's SRAM configuration cells before the FPGA enters user mode. Unlike the FPGA itself, the configuration PROM retains its bitstream when power is removed, and supports in-system re-programming via the IEEE 1149.1 (JTAG) interface or Altera's SRunner/PoE software chain. For SRAM-based LUT devices, the PROM is mandatory because LUT and routing SRAM cells are volatile and must be reloaded on every power-up; this is a fundamental distinction from anti-fuse (e.g., AX) or flash-based (e.g., MAX II CPLD) devices which do not require a separate boot memory. Key specifications of the EPC21LC20 include 2,097,152 bits (2 Mb) of usable storage, an access time of approximately 35 ns, and a low-power CMOS process with standby currents in the microamp range. Programming is performed via JTAG (IEEE Std 1149.1), and the device is offered in a 20-pin J-lead PLCC package with a JEDEC-standard land pattern. The 'LC' suffix denotes a 0 to 70 °C commercial temperature range; an 'LI' variant exists for industrial temperatures. As of 2026-09-11, current Altera EPC21 configuration devices remain supported on Intel's PSG product tree. Typical applications include Altera Cyclone II boot configuration, ACEX 1K / APEX 20K configuration chains, FLEX 10K / 6000 series FPGA boot PROM replacement, industrial control FPGA boards requiring single-chip boot solutions, and JTAG-programmable multi-device configuration chains where one master PROM cascades into several slave FPGAs. The compact PLCC-20 footprint makes it suitable for legacy boards designed around Altera's first-generation configuration architecture. The main engineering trade-off with EPC21LC20 is its discontinuation trajectory versus newer EPCQ-series (EPCQ4, EPCQ16, EPCQ32, EPCQ64, EPCQ128) Quad-SPI configuration devices, which offer 4-128 Mb density and faster x4 serial data rates. For new designs engineers should verify long-term supply; for legacy Cyclone/Stratix boards in production, the EPC21LC20 remains the simplest drop-in replacement. Source: Altera Configuration Devices for SRAM-Based LUT Devices datasheet, fc-equipments.com mirror.
EPC22C20N - Altera 20-Pin PLCC Configuration PROM | Intel
The Intel (formerly Altera) EPC22C20N is a 20-pin PLCC configuration PROM designed to load configuration data into SRAM-based LUT FPGAs such as the FLEX series. As a member of the EPC2 configuration-device family, it provides non-volatile storage for FPGA bitstreams, eliminating the need for external boot PROMs or microcontroller-driven configuration schemes. The device supports in-system programmability through the IEEE 1149.1 JTAG interface, allowing field updates without removing the device from the board. A configuration PROM is a specialized non-volatile memory device that stores the FPGA's bitstream and serially delivers it to the FPGA during power-up. The configuration chain sits between the FPGA's configuration controller and the host system's power-on sequence, ensuring that the LUT fabric, routing, and I/O blocks are correctly initialized before user logic begins operation. Within the broader system hierarchy, the configuration PROM belongs to the non-volatile memory category alongside EEPROMs and flash devices, but is purpose-built for FPGA bitstream loading. Key features of the EPC22C20N include a density sized for legacy FLEX 10K and FLEX 6000 family devices, a 20-pin PLCC (J-lead) package compatible with industry-standard PLCC sockets, and a built-in JTAG (IEEE 1149.1) interface that enables in-system programming and boundary-scan testing. The device operates from a single 3.3V or 5V supply, eliminating the need for external level translation. Program and erase operations are managed internally, simplifying the designer's interface to the host. The EPC22C20N employs a serial configuration architecture that uses a small number of FPGA pins (typically DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) to receive the bitstream. Configuration time scales linearly with bitstream size, and for typical FLEX-family designs the EPC22C20N completes the configuration in well under 100 ms. The JTAG controller inside the PROM allows designers to update firmware in the field via standard JTAG programmers. Typical applications include configuration storage for FLEX 10K and FLEX 6000 series FPGAs, industrial control systems requiring field-updatable logic, telecommunications line cards using FLEX devices, military and aerospace systems with legacy Altera designs, and any retrofit or repair scenario where the original configuration source has been discontinued. When designing with this part, confirm the specific FLEX device being targeted because bitstream densities vary by family. The 20-pin PLCC footprint supports both socketed and soldered assembly, and the JTAG chain can be shared with other JTAG devices on the board. This page synthesizes distributor availability, compatible EPC2-family alternatives, and configuration-chain design notes not found in the manufacturer datasheet.
EPC2L120 - 2.7V-3.6V 120Kbit Config Device | Altera | PLCC-20
The Altera EPC2L120 (formerly Intel Programmable Solutions Group) is a 2.7V to 3.6V low-voltage in-system programmable configuration memory device with a density of 120,160 bits (Kbit-class), housed in a 20-pin PLCC package. It is designed as a single-chip solution for configuring SRAM-based lookup-table (LUT) FPGAs such as Altera Cyclone, Cyclone II, and selected APEX families, eliminating the need for external boot PROMs or flash devices. Key specifications include an operating voltage range of 2.7V to 3.6V (3.3V typical), a storage capacity of 120 Kbit, in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, and a serial configuration interface that streams configuration data to the target FPGA. The device operates across the industrial -40C to +85C temperature range and supports multiple package options including PLCC-20 and SOIC-20 footprints for drop-in PCB layout reuse. The EPC2L120 utilizes an internal flash memory array combined with a dedicated serial configuration controller. Unlike older EPC1 devices, the EPC2 family adds 3.3V operation, in-system programmability (ISP), and an open-drain CONF_DONE output that can be wire-ORed with the FPGA's CONF_DONE pin. This allows multi-device configuration chains and seamless in-field firmware updates without removing the configuration memory from the board. Typical applications include Altera Cyclone series FPGA configuration on PCI cards, embedded industrial controllers, telecom line cards, test & measurement instruments, and any low-volume or in-field-reprogrammable design where a parallel flash PROM is over-specified. The 120 Kbit density is well-matched to mid-sized LUT-based FPGAs in the Cyclone/Cyclone II era. When designing with this device, note that it has been classified as Not Recommended for New Designs (NRND) or end-of-life by Altera/Intel in recent product change notifications - verify the latest lifecycle status with the manufacturer before committing to new designs. Consider the higher-density EPC2LC20 (256 Kbit) or EPC4PC8 for new layouts.
EPC2L1696-10F Altera Configuration Device for SRAM FPGAs | 1696-LUT
The Altera EPC2L1696-10F is a serial configuration EPROM designed to load configuration bitstreams into SRAM-based LUT devices (look-up table FPGAs). It supports logic densities up to 1,696 LUTs and uses a 5-pin serial interface (nCS, DCLK, DATA, OE, nINIT_CONF) that is directly compatible with Altera FLEX and APEX FPGA configuration schemes. Housed in a 20-pin PLCC package, it is rated for industrial-grade operation with the -10 speed grade indicating a 10 ns access time. A configuration device (also called a configuration PROM) is a non-volatile memory IC dedicated to storing and delivering FPGA configuration bitstreams at power-up. The hierarchy is: configuration PROM -> non-volatile memory -> memory IC -> semiconductor. In a typical boot sequence, the FPGA held in reset loads its configuration from the PROM over a synchronous serial link; once all bits have shifted in, the PROM releases OE and the FPGA enters user mode. This category is a predecessor to modern SPI flash + bitstream compression schemes used today, but legacy Altera designs still rely on it. Key features of the EPC2L1696-10F include 1,696 LUT-equivalent configuration density, 3.3 V single-supply operation, in-system programmability (ISP) through the JTAG-compatible 4-wire serial interface, and a programmable 'nINIT_CONF' pin that can re-trigger a configuration cycle without removing power. The 20-pin PLCC package is socket-friendly and easy to prototype, while supporting reflow profiles suitable for surface-mount production. Technically, the EPC2L1696-10F uses an internal CMOS EEPROM array with built-in address generation, so the host FPGA does not need to drive an explicit address bus - it simply clocks bits out on the rising edge of DCLK. This reduces FPGA pin-count pressure during configuration and keeps the boot BOM small. Program erase and rewrite cycles typically exceed 100,000 per the device family specification. Typical applications include Altera FLEX 10K / APEX 20K boot configuration, industrial PLC controllers, factory automation legacy systems, military and aerospace retrofits, and replacement / repair of legacy Altera reference designs. The -10 speed grade supports DCLK frequencies up to 100 MHz in cascade mode, which is sufficient for most FLEX-class devices. When designing with this part, note that the EPC2 family is a legacy Altera product line now supported through the Altera-to-Intel FPGA transition; verify current lifecycle status with authorized distributors before committing to a new design. For new designs, consider migrating to EPCQ or compatible SPI flash with the MAX II / MAX V CPLD configuration controller. This page synthesizes distributor pricing tiers, drop-in compatible variants from the same Altera EPC2 family, and practical design notes not consolidated in the original Altera datasheet.
EPC2L20 - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
The Altera EPC2L20 is a 1.6-Mbit in-system programmable configuration PROM designed to configure SRAM-based LUT devices such as Altera FPGAs in the APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, and Stratix families. The device is housed in a 20-pin J-lead PLCC package and operates from a 3.3 V core supply with 5.0 V or 3.3 V I/O tolerance. What is a configuration PROM? A configuration PROM is a non-volatile memory device that stores the bitstream for an SRAM-based FPGA. Because SRAM loses its configuration when power is removed, every SRAM-FPGA design requires a boot memory that delivers the bitstream on power-up via a serial or parallel configuration interface. The EPC2L20 belongs to the hierarchy: configuration PROM -> programmable logic support memory -> non-volatile memory -> semiconductor memory IC. Altera's EPC2 family replaced the older EPC1 family with higher density, in-system programmability via IEEE 1532, and lower power consumption. Key features include 1.6 Mbit of configuration storage organized as 8-bit bytes, in-system programmability through the JTAG (IEEE 1149.1 / IEEE 1532) interface, a cascadable multi-device daisy-chain architecture for higher density systems, and a low-power CMOS process. The device supports both 5.0 V and 3.3 V operation modes selectable via the VCCSEL pin, and integrates JTAG boundary-scan test capability for board-level manufacturability. The EPC2L20 uses a serial configuration interface that reduces FPGA pin-count overhead, and the cascadable architecture lets multiple EPC2 devices share a single configuration bus on the FPGA, allowing designers to scale up configuration density without changing the FPGA configuration controller. The 3.3 V core with 5 V tolerant I/O simplifies mixed-voltage board designs where older 5 V logic coexists with newer 3.3 V devices. Typical applications include Altera APEX II and APEX 20K configuration, Stratix and Cyclone FPGA boot memory, multi-FPGA configuration chains for DSP and prototyping boards, and industrial controllers using SRAM-based LUT devices. Engineers select the EPC2L20 when their FPGA configuration bitstream fits within 1.6 Mbit and they require the simplicity of a single-chip configuration solution. Designers should verify that their compiled FPGA bitstream does not exceed 1.6 Mbit before selecting this device, and ensure that the JTAG chain is correctly terminated for in-system reprogramming. For higher densities, EPC4 or EPC8/EPC16 in the same family provide more storage in larger packages. This page synthesizes distributor pricing across Nantian, Veswin, Jotrin and FPGAkey alongside pin-to-pin compatible alternatives in the Altera EPC2 family not found in the standalone datasheet.
EPC2L20N - 1.6Mb Altera FPGA Config PROM | PLCC-20
The Intel (formerly Altera) EPC2L20N is a 1.6-Mbit in-system-programmable configuration PROM designed to load the configuration bitstream into SRAM-based LUT FPGAs such as the APEX, ACEX, Cyclone, FLEX 10K, and Mercury device families. The part is offered in a 20-pin J-lead PLCC (PLCC-20) package that supports either 3.3 V (3.0 V to 3.6 V) or 5.0 V (4.5 V to 5.5 V) operation, allowing it to drive FPGA configuration pins directly without external level shifting. What is a configuration PROM? A configuration PROM is a non-volatile serial memory that stores the FPGA's configuration bitstream and serially shifts it into the FPGA during power-up or reconfiguration. It sits between the system flash and the FPGA in the boot hierarchy: microprocessor -> flash -> configuration PROM -> SRAM-based FPGA. By isolating the bitstream from system flash, the PROM lets engineers update FPGA firmware in-system without recompiling the host firmware. The EPC2L20N uses an in-system-programmable (ISP) interface so the bitstream can be reloaded through JTAG-style four-wire programming without removing the device from the board. Cascading of multiple PROMs is supported via the chip-enable control to handle configuration images larger than 1.6 Mb, which historically let designers support Cyclone II and APEX 20K designs. Internal oscillator and clock-management circuitry generate the serial configuration clock for the target FPGA. The PLCC-20 (J-lead) package is through-hole-compatible and socket-compatible, allowing easy field replacement and prototype iteration. Operating temperature spans the commercial 0C to +70C range as the standard grade, with industrial-grade variants available for harsher environments. Typical applications include Altera FPGA configuration bitstream storage for industrial control boards, telecom line cards, prototyping platforms, and embedded compute modules where the SRAM-based LUT FPGA must be reconfigured at power-up. When designing with this device, observe Altera's configuration interface timing requirements and verify the cascaded PROM chain supports the total bitstream length for the chosen FPGA family. For new designs, designers should evaluate newer serial configuration devices, as the EPC2 family has been in mature production for many years. This page synthesizes Altera/Intel configuration-device specifications, distributor availability and pricing, drop-in alternatives, and engineering notes not consolidated in any single manufacturer document.
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
The Intel (formerly Altera) EPC2L20U-HAF480119C is a 1.6 Mb in-system-programmable configuration PROM designed to load configuration bitstreams into SRAM-based LUT FPGAs such as the Cyclone, Stratix, and APEX families. Built on a 3.3 V core with 5 V tolerant I/O, the device supports serial (1-bit) and parallel (8-bit) configuration data paths and packages the configuration memory in a compact 20-pin PLCC (HAF480119C designation refers to the factory-programmed configuration image suffix and package code). A configuration PROM is a non-volatile memory device whose sole purpose is to store and stream the FPGA's bitstream to the FPGA at power-up. The EPC2 family sits inside the broader hierarchy of FPGA configuration devices: configuration PROM -> non-volatile memory -> semiconductor memory -> integrated circuit. Unlike boot PROMs for microcontrollers, EPC2 devices support in-system reprogrammability via JTAG, IEEE 1149.1 boundary-scan, or dedicated serial/parallel data pins, enabling field updates of the FPGA bitstream without removing the board. Key features include 1.6 Mb of storage capacity, support for FPGAs up to the Cyclone IV and Stratix IV device densities, cascadable JTAG chains for multi-FPGA systems, and an open-drain nSTATUS / CONF_DONE handshake for synchronous configuration completion detection. The EPC2 supports compression-mode bitstreams, allowing the PROM to hold a compressed image that the FPGA decompresses on load, effectively increasing usable capacity by 35-50% depending on the FPGA family. Technically, the EPC2L20 implements Altera's proprietary serial configuration state machine with automatic baud-rate detection between 10 MHz and 40 MHz. Its 20-pin PLCC footprint allows socketed field replacement, which simplifies legacy system maintenance. Compared with newer EPCQ/Avalon-ST configuration devices, the EPC2L20 retains a mature JTAG programming interface that aligns with legacy Quartus II design flows. Typical applications include factory provisioning of Cyclone II/III FPGAs in industrial controllers, Stratix II design prototype boards, broadcast video processing equipment, and legacy aerospace/defense systems that standardized on EPC2 in the 2000-2010 era. The PLCC-20 socketed form factor allows easy inspection and replacement in long-lifecycle programs. When designing with EPC2L20, verify that the target FPGA's configuration scheme matches EPC2L20's supported modes (FPP x8 at 40 MHz, PS, AS, JTAG). For newer Cyclone V / Stratix V devices, migrate to EPCQ256 or active serial flash, as EPC2 supports only legacy configuration controllers. This page synthesizes distributor stock checks, real-time pricing tiers, and pin-compatible alternatives in the same PLCC-20 footprint, providing engineering context not consolidated on the manufacturer datasheet alone.
EPC2LC120 - PLCC-120 Altera FPGA Config Device | Intel
The Altera (now Intel) EPC2LC120 is a 120-pin PLCC Configuration Device designed for programming and configuring SRAM-based look-up table (LUT) FPGAs, including the FLEX, ACEX, APEX, and Mercury families. It provides non-volatile storage of the FPGA configuration bitstream with in-system programmability via JTAG and supports flexible configuration schemes such as serial (PS), parallel (PPA), and multi-device daisy-chaining. The EPC2LC120 is rated for commercial operating temperatures and is supplied in a JEDEC-standard 120-lead plastic leaded chip carrier (PLCC-120) socketed package for field upgrades and manufacturing rework. A configuration device is a non-volatile memory IC that holds the FPGA configuration bitstream and presents it to the target FPGA at power-on via a structured handshake protocol (typically Altera's FPP or PS scheme). It sits in the FPGA boot hierarchy as the third tier: below JTAG-direct programming and below processor-driven configuration, but above the absent-on-board-boot-PROM option. EPC2 devices are specifically tailored to Altera's proprietary configuration state machine, exposing CONF_DONE, nSTATUS, nCONFIG, and DCLK signals that handshake with the FPGA. Unlike generic SPI flash, the EPC2 family integrates compression, error-checking, and remote update logic. Key features of the EPC2LC120 include 2 Mbit (approximately 250 Kbyte) configuration storage density, byte-wide or serial configuration data width selectable per design, 3.3V single-supply operation, JTAG IEEE 1149.1 boundary-scan compliance for in-system programming, and a small footprint PLCC-120 package with socket compatibility for field replacement. The device supports multi-device configuration chains, enabling a single EPC2 to program multiple FPGAs in parallel or serial mode depending on the system architecture. From an architectural standpoint, the EPC2LC120 uses an embedded CMOS non-volatile memory cell array with on-chip charge pumps and a serial/parallel configuration controller. The integrated controller handles Altera's proprietary configuration handshaking and supports optional compression (up to 2:1) of the stored bitstream, effectively doubling usable density. The device also supports remote update via the Altera multi-mode configuration protocol, allowing firmware revisions over JTAG without removing the device from the board. Typical applications include legacy Altera FLEX 10K/ACEX 1K/APEX 20K series FPGA configuration, industrial control boards with field-upgradable logic, military and aerospace systems using older Altera silicon, and prototyping platforms where the configuration memory must be hot-swappable. The PLCC-120 socket makes it well suited to engineering development environments where configuration files change frequently. When designing with the EPC2LC120, ensure the JTAG chain order is correct so that the EPC2 is programmed as a slave device alongside the FPGA. Decoupling caps (0.1uF ceramic placed adjacent to each VCC pin) are recommended to handle the in-system programming write currents. Confirm the FPGA configuration mode (FPP/PS/PPA) matches the EPC2 data-width setting in the Quartus configuration editor.
EPC2LC20 - 1.6Mb In-System Prog Config PROM 20-PLCC | Altera
The Altera EPC2LC20 is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed to load configuration bitstreams into SRAM-based Altera FPGA families at power-up. Housed in a 20-pin J-lead PLCC (9x9 mm) package, the EPC2LC20 supports configuration data widths of x1 in serial mode and connects directly to Altera FPGAs such as ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, and MAX 9000 series. The device is rated for both 5.0-V and 3.3-V ISP through the built-in IEEE 1149.1 (JTAG) Test Access Port (TAP), enabling reconfiguration in-circuit without removing the device from the board. A configuration PROM is a non-volatile memory device that stores the FPGA's configuration bitstream and delivers it serially or in parallel to the target SRAM-based FPGA every time the system powers up or when new configuration data is needed. Because SRAM-based LUT devices are volatile, the EPC2LC20 eliminates the need for a separate boot ROM and reduces BOM cost, PCB area, and design complexity. The EPC2 family sits in the broader hierarchy of FPGA configuration memory: configuration PROM -> non-volatile boot memory -> FPGA companion IC -> programmable logic support silicon. Key features of the EPC2LC20 include 1.6 Mbits of storage capacity, cascadable JTAG-chain support so multiple EPC2 devices can be chained together to configure larger FPGAs, and dedicated open-drain CONF_DONE and nSTATUS pins for handshaking with the target FPGA. The device supports 8-bit or 16-bit JTAG boundary-scan, plus built-in data decompression compatible with Altera Quartus II programming files. Programming is performed via the Altera Programming Unit (APU) or any IEEE 1149.1-compliant JTAG controller. In terms of architecture, the EPC2LC20 is built around a CMOS non-volatile memory array with on-chip charge pumps for ISP operation. It exposes standard JTAG pins (TCK, TMS, TDI, TDO) plus dedicated nCONFIG, nSTATUS, CONF_DONE and DCLK interface pins to the FPGA, so no glue logic is required between the PROM and the FPGA. The JTAG-based ISP allows field upgrades and factory-floor programming using only a 4-wire JTAG cable. Typical applications include boot configuration for Cyclone and Cyclone II FPGA designs, APEX 20K family prototyping cards, multi-FPGA systems that daisy-chain several EPC2 devices in JTAG order, industrial controllers using FLEX 10K/6000 logic, and legacy designs that require a simple non-volatile companion to Altera SRAM-based FPGAs. When selecting between EPC2 variants, choose the EPC2LC20 for low-density designs and cascade additional EPC2s for larger FPGA bitstreams.
EPC2LC20-T - 1.6Mb FPGA Config PROM PLCC-20 | Altera
The Altera (Intel) EPC2LC20-T is a 1.6 Mb in-system programmable Configuration PROM for SRAM-based FPGAs, housed in a 20-pin PLCC package. It operates at up to 10 MHz serial configuration frequency and supplies non-volatile storage for Altera SRAM-LUT devices such as the ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, and Mercury families. The "-T" suffix indicates tape-and-reel packaging for high-volume surface-mount assembly. A Configuration PROM is a serial non-volatile memory that loads bitstream data into an SRAM-based FPGA at every power-up, because SRAM configuration cells are volatile. EPC2-series PROMs sit between the system's flash storage or microcontroller and the FPGA's DATA0/DCLK/nCONFIG/nSTATUS/CONF_DONE pins, presenting the bitstream serially via Altera's FPP or PS configuration schemes. This category sits inside the broader hierarchy: non-volatile memory -> PROM -> configuration memory -> FPGA boot device -> semiconductor. Key features of the EPC2LC20 include 1.6 Mb flash storage, in-system programmability through the JTAG IEEE Std 1149.1-1990 boundary-scan interface, and the ability to cascade multiple devices to support larger bitstreams. The device operates from a single 3.3 V supply and integrates a low-voltage detector that holds the FPGA in reset until VCC is stable, simplifying multi-rail power sequencing. The EPC2 uses a 4-pin serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) compatible with Altera's PS configuration mode. Internally, a state machine manages configuration timing, CRC checking, and optional data compression. The JTAG port supports ISP (In-System Programming) so designers can update firmware in the field without removing the PROM. Typical applications include industrial control boards, military and aerospace FPGA systems, telecommunications line cards, medical imaging hardware, and test-and-measurement equipment using Altera/Intel FPGAs. The wide JTAG support also makes the EPC2LC20-T well suited for remote firmware updates. Design consideration: Because EPC2-series PROMs are pre-loaded via JTAG or the Altera Programming Unit, plan ISP access through the FPGA's JTAG chain or a dedicated header. When cascading multiple EPC2s, the nCASC pin propagates enable to the next device in the chain. This page consolidates distributor pricing, drop-in pin-compatible alternatives, and engineering design notes that extend beyond the original Altera datasheet.
EPC2LC20-U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera (Intel)
The Altera EPC2LC20-U is an in-system programmable configuration PROM designed to load configuration bitstreams into Altera/Intel SRAM-based FPGAs at power-up, delivering 1.6 Mb of flash-backed configuration storage in a 20-pin PLCC (9x9) package with 10 MHz serial interface speed. It supports 3.3V operation and includes JTAG-based in-system programmability (ISP) via the IEEE 1149.1 boundary-scan chain, eliminating the need for an external programmer. A configuration PROM is a non-volatile memory device dedicated to storing the FPGA bitstream. On every power-up the FPGA's SRAM configuration cells must be reloaded because SRAM is volatile; the EPC2 family is purpose-built for this task and connects to the FPGA's dedicated serial configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). Compared with generic SPI flash, configuration PROMs reduce board complexity by offering a guaranteed-timing, drop-in storage device for legacy Altera APEX, FLEX, Cyclone, ACEX and Arria GX families. Key features include 1.6 Mb storage (sufficient for mid-density FPGAs), a 10 MHz serial configuration clock, in-system programmability via JTAG, cascadable architecture for larger bitstreams, and a low pin count 20-PLCC footprint that simplifies PCB layout. The device operates from 3.0V to 3.6V across the industrial -40C to +85C range. The EPC2 uses a 4-pin serial interface plus JTAG, with on-chip voltage generation for the program/erase charge pump and a built-in oscillator for internal timing. The cascadable feature allows two or more EPC2 devices to be chained to configure larger FPGAs, with the master/slave handoff handled automatically over the serial interface. Typical applications include legacy Altera APEX 20K / APEX II / ACEX 1K / FLEX 10K configuration, Cyclone and Cyclone II boot memory, Arria GX configuration, industrial control cards that pair a small FPGA with non-volatile storage, and any 3.3V system that needs reliable in-system reprogrammable configuration memory. The JTAG ISP capability also supports field firmware updates without removing the board. When designing with this part, place a 0.1 uF decoupling capacitor within 5 mm of VCC and keep the JTAG chain length under about 150 mm to preserve signal integrity. For bitstreams larger than 1.6 Mb, cascade a second EPC2 device - the FPGA's MSEL pins select the cascade mode and CONF_DONE handling is automatic. This page synthesizes distributor stock, verified drop-in alternatives such as EPC2LI20 and EPC2LC20N, lifecycle status, and design considerations not found in the bare datasheet.
EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
The Altera (Intel) EPC2LC20-V is a 1.6-Mbit in-system programmable Configuration PROM designed for configuring SRAM-based look-up table (LUT) FPGAs, housed in a 20-pin Plastic Leaded Chip Carrier (PLCC) package optimized for legacy through-hole and socketed production flows. A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and loads it into the SRAM-based LUT device at power-up, reset, or upon reconfiguration request. Within the broader hierarchy, configuration PROMs sit at the boot-memory layer beneath FPGAs and CPLDs, between power-on reset events and the user logic — EPC1/EPC2 series parts specifically support Altera (now Intel) APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, and MAX 9000 device families, simplifying single-chip configuration and enabling remote in-system reconfiguration via JTAG. Key features include 1.6 Mbit of Flash-based configuration storage, a serial configuration interface clocked up to 10 MHz, in-system programmability through the IEEE 1149.1 (JTAG) boundary-scan port, and a cascadable daisy-chain interface that allows multiple EPC2 devices to be linked for designs exceeding the single-device capacity. The -V suffix indicates the commercial operating temperature range of 0 °C to +70 °C, while the LC family provides the low-cost tier of the EPC2 line. Technically, the EPC2LC20-V uses a 3.3 V core supply (VCC) with 5 V-tolerant I/O on configuration interface pins, four JTAG pins (TMS, TCK, TDI, TDO) supporting boundary-scan and ISP, and dedicated nCS, nSTATUS, CONF_DONE, and DCLK pins for the FPGA configuration handshake. The 20-pin PLCC package (JEDEC MS-018) provides a socket-friendly footprint suitable for prototyping sockets, field upgrades, and legacy replacement scenarios. Typical applications include configuring APEX 20K and ACEX 1K FPGA prototype boards, industrial control systems with field-upgradable logic, telecommunications line cards using FLEX 10K devices, and military/aerospace ground-test fixtures built around MAX 9000 parts. The 1.6 Mbit density is dimensioned for mid-density APEX 20K designs and most ACEX 1K configurations. Designers should budget for the dedicated JTAG header and ensure that the PROM-to-FPGA DCLK/nSTATUS/CONF_DONE handshake traces are kept short. For multi-PROM cascading, ensure that the cascaded chain does not exceed the FPGA's maximum configuration clock frequency or supported PROM count. This page consolidates distributor pricing, drop-in alternatives in the same 20-PLCC footprint, and practical design considerations not directly summarized in the Altera configuration-device datasheet — distinct information gain relative to manufacturer PDF and Octopart listings.
EPC2LC20CAD - 1.6Mb Config PROM for SRAM FPGAs | Altera
The Altera EPC2LC20CAD is a 1.6 Mb in-system programmable configuration PROM designed to load configuration data into SRAM-based Altera FPGAs such as the APEX, ACEX, Cyclone, and Stratix device families. It is housed in a 20-pin J-lead PLCC (PLCC-20) package and operates from a single 3.3V supply. The device supports serial (bit-wide) configuration of single FPGAs through a dedicated serial-data interface and can be cascaded for multi-device chains. An FPGA configuration PROM is a non-volatile memory device whose sole purpose is to store the bitstream image that an SRAM-based LUT FPGA needs at every power-up because SRAM cells lose their configuration when power is removed. The EPC2 family sits in the boot-memory hierarchy between the FPGA and the system host: at power-on the FPGA reads its bitstream serially from the PROM, then enters user mode. Modern Altera/Intel parts replaced the EPC2 family with active serial (AS) flash configuration devices, so the EPC2LC20CAD is now widely used as a drop-in legacy replacement and for repair/maintenance of installed systems. Key features include 1.6 Mb storage capacity, in-system programmability through the IEEE Std 1149.1 JTAG interface, 3.3V single-supply operation with 5V tolerant I/O, and a JTAG-based ISP that allows the bitstream to be updated on-board without removing the device. Programming is performed through the standard JTAG pins (TCK, TMS, TDI, TDO) so no dedicated programmer socket is required, simplifying manufacturing flow. The EPC2 architecture is a serial Flash PROM optimized for one-time-or-occasional update use rather than high-endurance writes. Internally it contains an oscillator, address counter, and serial interface state machine that streams the configuration bits to the FPGA. The 20-pin PLCC package provides a through-hole or socketed footprint that was standard for late-1990s and early-2000s Altera reference designs. Typical applications include Altera APEX 20K, ACEX 1K, Cyclone (original), and Stratix FPGA configuration in industrial controllers, telecommunications line cards, and legacy networking equipment. The device is also used in test fixtures and as a repair/maintenance part for legacy Altera boards where the original configuration PROM has failed or needs to be re-programmed. When designing with this device, ensure the JTAG chain is properly terminated and that the PROM's nSTATUS/CONF_DONE handshaking matches the target FPGA's configuration mode. The 3.3V supply must be stable before the FPGA releases its nCONFIG signal, otherwise the FPGA may enter an undefined state and require re-configuration. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone, providing engineers with a single reference for sourcing and replacement decisions.
EPC2LC20ES - 1.6Mb ISP Config PROM for FPGAs | Intel / Altera
The Intel (formerly Altera) EPC2LC20ES is an in-system programmable (ISP) configuration memory device designed for SRAM-based FPGAs and LUT devices, providing 1.6 Mbit of non-volatile storage in a 20-pin PLCC (J-lead) package. The device stores configuration bitstreams that are loaded into the FPGA's SRAM configuration cells at power-up, and supports 5.0 V and 3.3 V operation including in-system programmability through the built-in IEEE Std. 1149.1 JTAG interface. The EPC2LC20ES is functionally equivalent to the EPC2LC20 with the "ES" suffix denoting a specific lead-free or industrial temperature grade variant. A Configuration PROM (Programmable Read-Only Memory) for FPGAs is a non-volatile serial memory device that holds the FPGA's configuration bitstream. When the FPGA powers up, it reads its configuration data from the PROM via a serial or parallel configuration interface. These devices sit in the broader memory hierarchy as: PROM -> non-volatile memory -> configuration memory -> FPGA support IC, and are essential for standalone FPGA designs that need to self-configure without an external microprocessor or download cable. Key features of the EPC2LC20ES include 1.6 Mbit storage capacity suitable for mid-density Altera FPGAs such as the ACEX 1K, APEX 20K, Cyclone, and Mercury families, JTAG-based ISP that allows field upgrades without removing the device, and built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1. The device supports both DCLK-based serial and parallel configuration modes, providing flexibility across multiple FPGA targets. Low standby current and 3.3 V/5 V tolerance make it well suited for mixed-voltage system designs. Architecturally, the EPC2LC20ES uses a serial interface with a built-in oscillator and state machine that streams configuration data to the FPGA through the DATA, DCLK, and nCONFIG/nSTATUS control signals. The on-chip JTAG TAP controller enables both ISP and boundary-scan test access. The PROM operates as a slave device on the JTAG chain, allowing multiple devices to be programmed and verified in a single boundary-scan pass. Typical applications include configuration storage for Altera ACEX 1K, APEX 20K, Cyclone, Mercury, and Stratix-class FPGAs, factory-floor JTAG programming stations, and field-upgradable embedded systems. Designers also use this PROM in industrial controllers and military/aerospace prototypes where a self-booting FPGA is required without an external configuration controller. When designing with this device, note that the EPC2LC20ES is rated for industrial temperature range and ships as a lead-free PLCC-20 J-leaded package for through-hole or socketed mounting. The device is in production but considered a legacy Altera configuration solution; for new designs, designers should evaluate Altera/Intel EPCQ-series serial configuration devices (AS mode) for newer FPGA families. This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers quickly validate EPC2LC20ES as a configuration memory solution for legacy and current Altera FPGA designs.
EPC2LC20N - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
The Intel (formerly Altera) EPC2LC20N is a 1.6-Mbit in-system programmable Flash configuration PROM designed to load configuration bitstreams into SRAM-based LUT FPGAs at every power-up. Housed in a 20-pin PLCC (J-lead, 9x9 mm) package, it operates from dual-rail supplies of 3.0 V to 3.6 V and 4.75 V to 5.25 V, supports JTAG-ISP (IEEE 1532 / IEEE 1149.1) and Altera serial configuration modes, and runs the configuration clock up to 8 MHz. A configuration PROM (Programmable Read-Only Memory) is a non-volatile serial memory device whose sole purpose is to store the bitstream for an SRAM-based programmable logic device. Because SRAM-LUT FPGAs are volatile, their configuration must be reloaded on every power-up or reconfiguration event; the EPC2 family performs that role in a single-chip solution, replacing discrete EPROMs, microcontrollers, or boot-PROM arrangements. EPC2 devices sit in the boot-source hierarchy beneath FPGAs (CPLD -> glue logic -> PROM -> FPGA) and are an integral part of the Altera/Intel FPGA power-on sequencing ecosystem. Key features of the EPC2LC20N include 1.6 Mbit of Flash storage, in-system programmability via JTAG, a built-in 8 MHz internal oscillator, and support for both 3.3 V and 5 V supply rails. It also provides a dedicated nSTATUS, nCONFIG, and CONF_DONE handshake to the target FPGA, eliminating the need for external glue logic in most designs. The EPC2LC20N uses a 4-pin serial interface (DATA0, DCLK, nCONFIG, nSTATUS) to cascade-multiple PROMs can be chained to support larger FPGAs. The device supports FPGAs from the Altera APEX, Cyclone, Stratix, ACEX, and MAX 7000 families, with automatic baud-rate detection between the PROM and target device. Typical applications include Altera/Intel Cyclone and APEX prototype boards, industrial control logic, telecom base-station FPGA boot cards, military/aerospace FPGA subsystems, and any system requiring multi-configuration support. The in-system programmability allows field upgrades without removing the PROM from the board. When designing with this device, ensure proper decoupling (0.1 uF + 10 uF) on both VCC rails and respect the JTAG chain order if multiple PROMs are cascaded. The 5 V rail tolerance simplifies designs that mix 3.3 V FPGA I/O with 5 V configuration memory logic. This page synthesizes distributor stock levels, drop-in Altera/Intel PROM alternatives, and JTAG-chain design notes not found on the original manufacturer datasheet.
EPC2LC20N-W - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
The Intel/Altera EPC2LC20N-W is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed for serial configuration of SRAM-based LUT FPGAs such as APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, and Cyclone families. It is supplied in a 20-pin PLCC (J-lead) package with a 3.0V-3.6V or 4.75V-5.25V dual-rail supply range and supports 66.7 MHz internal oscillator-based serial data delivery. The "-W" suffix denotes the tape-and-reel packaging option of the base EPC2LC20N part. A configuration PROM is a non-volatile memory that stores FPGA bitstream data and serially transfers it to the target FPGA at power-up via the DATA, DCLK, OE, and nCS handshake lines. In the broader hierarchy, the EPC2 sits under Altera's enhanced-configuration-device family (EPC4/EPC8/EPC16/EPC2/EPC1/EPC1441), which itself belongs to the FPGA-support ecosystem (configuration memory -> memory IC -> semiconductor). The 3.3V/5V dual supply, JTAG ISP support, and 1.6-Mbit density make the EPC2LC20N-W one of the most widely used legacy Altera configuration devices. Key features include 1.6 Mbit EPROM density, serial configuration clock up to 66.7 MHz, in-system programmability through the JTAG (Joint Test Action Group) interface, 4-pin serial interface (DATA, DCLK, nCS, OE), and support for cascading with other EPC devices. The device is non-cascadable in the enhanced-configuration-device family when targeting newer high-density Stratix FPGAs; for those applications Altera recommends EPC4/EPC8/EPC16. The EPC2LC20N-W uses an EPROM core that is erased by UV exposure (windowed package variants) and reloaded via JTAG. The internal address counter is clocked by DCLK from the target FPGA, while nCS and OE gate the tri-state DATA output. The combination of a small footprint and a robust serial protocol has made the EPC2 a de-facto standard for APEX 20K and ACEX 1K designs. Typical applications include APEX 20K / ACEX 1K / FLEX 10K FPGA boot configuration, Stratix-series configuration on legacy boards, industrial control system FPGA boot memory, and test equipment FPGA bitstream storage. For designs migrating to Cyclone III/IV/V or Stratix V/10, Altera recommends newer configuration devices or active serial flash. Designers should verify that the target FPGA is compatible with the EPC2 device family using the Altera Configuration Device Compatibility table before PCB layout. The 20-pin PLCC J-lead package requires a socket or reflow profile compatible with J-leaded devices. This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not found in the manufacturer datasheet. Lifecycle, supply voltage, and pinout values are extracted verbatim from the Altera EPC2 Configuration Devices datasheet.