5CSEBA2U19I7N vs 5CSEBA2U19C8N Comparação
Comparação detalhada lado a lado de 5CSEBA2U19I7N por Intel e 5CSEBA2U19C8N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 5CSEBA2U19I7N | 5CSEBA2U19C8N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $445,65 | $52,40 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25K | — |
| HPS | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Clock Frequency | 800 MHz | — |
| Embedded Memory | 1,400 Kbits | — |
| DSP Blocks (18x18 Multipliers) | 66 | — |
| User I/O Pins | 145 | — |
| LVDS Support | Up to 1.25 Gbps | — |
| Encapsulamento | 484-UBGA (19x19 mm) | 484-pin UBGА (19x19 mm) |
| Process Technology | 28 nm TSMC low-power | 28 nm low-power |
| Temperatura de operação | -40C to +100C (Industrial) | 0C to +85C (commercial) |
| Voltage - Input (Max) | 1.1 V core | — |
| Peripherals | USB 2.0 OTG, Gigabit Ethernet, CAN, UART, SPI, I2C, NAND/NOR flash controllers | — |
| HPS-FPGA Interconnect | AXI bridges (3 master / 3 slave), FPGA-to-HPS SDRAM, DMA | — |
| Status RoHS | Compliant | Compliant |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount |
| Series | — | 5CSEA2 |
| Device Variant | — | 5CSEBA2 (25K logic elements, dual ARM Cortex-A9) |
| Core Architecture | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 600 MHz |
| FPGA Logic Elements | — | 25,000 |
| Embedded Memory (M10K) | — | 1,400 Kb (typical for 25K LE variant) |
| DSP Blocks | — | Variable-precision DSP |
| Core Supply Voltage | — | 1.1 V |
| Memory Controller Support | — | DDR2, DDR3, LPDDR2 |
| High-Speed Transceivers | — | Present (Cyclone V SE family feature) |
| PLLs | — | Multiple (per Cyclone V SE device handbook) |
| Nível MSL | — | 3 (per JEDEC J-STD-020, assumed for 484-BGA) |