5CSEBA6U23I7LN vs 5CSEBA6U23I7N Comparação
Comparação detalhada lado a lado de 5CSEBA6U23I7LN por Intel e 5CSEBA6U23I7N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 5CSEBA6U23I7LN | 5CSEBA6U23I7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $184,83 | $51,80 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 110,000 | 110,000 |
| Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum CPU Clock | 925 MHz | — |
| Encapsulamento | 672-pin UBGA (UBG-672) 23x23 mm | 672-UBGA (UBG A-672) 23x23 mm |
| Tipo de montagem | Surface Mount (BGA) | — |
| Speed Grade | I7 (fast) | 7 |
| Temperature Range | Industrial (-40C to +100C junction) | — |
| Suffix L | Lead-free | — |
| Suffix N | Tray packaging | — |
| Status RoHS | Compliant (lead-free suffix) | — |
| Hard Memory Blocks | [DATA_NEEDED: total M10K and MLAB bits] | — |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP block count] | 224 (variable-precision) |
| HPS Peripherals | Gigabit Ethernet, USB 2.0 OTG, CAN, SPI, I2C, UART, SD/SDIO | — |
| Configuration Mode | JTAG and Active Serial (AS) | — |
| Process Node | TSMC 28 nm low-power | — |
| Design Toolchain | Intel Quartus Prime + SoC EDS | — |
| Process Technology | — | 28 nm TSMC low-power |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| Embedded Memory | — | 5,662 Kbits (M10K + MLAB) |
| Maximum User I/O | — | 364 |
| Core Voltage | — | 1.1 V |
| Temperatura de operação | — | -40C to +100C (industrial, junction) |
| Temperature Grade | — | Industrial (I) |
| Lead-Free / RoHS | — | Yes (Pb-free, N suffix) |
| DDR Controller | — | 32-bit DDR3/LPDDR2 with ECC |
| Configuration | — | FPGA + HPS integrated SoC |