5M570ZT144A5N vs 5M1270ZT144C5N Comparação
Comparação detalhada lado a lado de 5M570ZT144A5N por Intel e 5M1270ZT144C5N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AtivoComparação de especificações
| Parâmetro | 5M570ZT144A5N | 5M1270ZT144C5N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $10,40 | $12,45 |
| Family | MAX V | — |
| Series | 5M570Z | MAX V |
| Macrocells | 440 | 980 |
| User I/Os | 114 | 114 |
| Logic Array Blocks (LABs) | 44 | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V | — |
| Propagation Delay (tPD) | 17.7 ns | — |
| Maximum User Frequency | [DATA_NEEDED: maximum fMAX] | — |
| Configuration Technology | Non-volatile Flash | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| In-System Programmability | Yes (via JTAG) | — |
| Standby Current (typical) | 27 µA | — |
| Temperatura de operação | -40 °C to +125 °C (industrial) | 0 C to +85 C (commercial grade) |
| Encapsulamento | TQFP-144 (T144), 0.5 mm pitch, 20 mm × 20 mm | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Process Technology | CMOS | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Lead Free / RoHS | Yes (RoHS compliant, -N suffix) | — |
| Moisture Sensitivity Level | MSL 3 | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 1270 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| Configuration Memory | — | Flash (non-volatile, in-system programmable) |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Programming Interface | — | JTAG in-system programmable (Altera Quartus II) |
| Program/Erase Cycles | — | Up to 100,000 |
| Status RoHS | — | Compliant |