EP1810GC-35AB vs EP1810JC-25 Comparação
Comparação detalhada lado a lado de EP1810GC-35AB por Altera e EP1810JC-25 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810GC-35AB | EP1810JC-25 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,95 | $6,80 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable (windowed ceramic DIP) |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Maximum Toggle Frequency | 62.5 MHz | [DATA_NEEDED: max fMAX] |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | -40 °C to 85 °C (industrial, per distributor listings) |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Encapsulamento | — | 28-pin ceramic DIP (J) with quartz window |
| Tipo de montagem | — | Through-hole |
| Erasure Method | — | UV light (windowed package) |
| Status do ciclo de vida | — | NRND (Not Recommended for New Designs) |