EP1810JC35 vs EP1810JC-45 Comparação
Comparação detalhada lado a lado de EP1810JC35 por Altera e EP1810JC-45 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810JC35 | EP1810JC-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,75 | $21,10 |
| Family | Altera Classic EPLD | EP1810 (Classic EPLD Family) |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | — |
| Frequência máxima de clock | 40 MHz | 33.3 MHz |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| Temperatura de operação | 0 C to +70 C (Commercial) | — |
| Encapsulamento | PLCC-68 (J-lead, ceramic) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Package Code | QCCJ | QCCJ |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Technology | — | CMOS, UV-erasable |
| Maximum Supply Voltage | — | 5.25 V |
| Contagem de pinos | — | 68 |
| Temperature Grade | — | Commercial |
| Tipo de montagem | — | Surface Mount |