EP1810JC35 vs EP1810JC-45 비교
다음의 상세 나란히 비교: EP1810JC35 제조: Altera 및 EP1810JC-45 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC35 | EP1810JC-45 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $21.10 |
| Family | Altera Classic EPLD | EP1810 (Classic EPLD Family) |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | — |
| 최대 클록 주파수 | 40 MHz | 33.3 MHz |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 동작 온도 | 0 C to +70 C (Commercial) | — |
| 패키지 | PLCC-68 (J-lead, ceramic) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Package Code | QCCJ | QCCJ |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Technology | — | CMOS, UV-erasable |
| Maximum Supply Voltage | — | 5.25 V |
| 핀 수 | — | 68 |
| Temperature Grade | — | Commercial |
| 실장 유형 | — | Surface Mount |