EP1810LI-25 vs EP1810LC-25 Comparação

Comparação detalhada lado a lado de EP1810LI-25 por Altera e EP1810LC-25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP1810LI-25 EP1810LC-25
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $9,95 $8,40
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device), UV-erasable / OTP —
Macrocells 48 48
Usable Gates 900 —
Propagation Delay (tPD) 25 ns 25 ns
Maximum Counter Frequency 40 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) 5 V (TTL-compatible)
I/O Pins 48 48
Dedicated Inputs 12 12
Global Clock Inputs 4 —
Interconnect Programmable global and local buses —
Encapsulamento 68-pin PLCC (J68, J-Lead) 68-pin JLCC (J-leaded ceramic chip carrier)
JESD-30 Package Code S-PQCC-J68 —
Process Technology CMOS —
Operating Temperature (Industrial 'I' suffix) -40 C to +85 C —
Programming Mode EPROM/UV-erasable (windowed) and OTP —
Development Tool Altera MAX+PLUS II —
Status RoHS unknown [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Lead-Free Status unknown —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
External Clock Inputs — 4
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Tipo de montagem — Surface Mount
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Status do ciclo de vida — Obsolete (legacy Altera Classic family)
Temperatura de operação — [DATA_NEEDED: temperature grade for LC package]

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