EP1810LI-25 vs EP1810LI-45 Comparação
Comparação detalhada lado a lado de EP1810LI-25 por Altera e EP1810LI-45 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ AtivoComparação de especificações
| Parâmetro | EP1810LI-25 | EP1810LI-45 |
|---|---|---|
| Marca | Altera | Rochester Electronics |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,95 | $64,10 |
| Family | Altera Classic EPLD | Altera Classic |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | — |
| Macrocells | 48 | 48 |
| Usable Gates | 900 | 900 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | — |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| Encapsulamento | 68-pin PLCC (J68, J-Lead) | 68-pin PLCC / PQCC68 (J-Lead) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | — |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | unknown | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Technology | — | CMOS, UV-erasable EPROM configuration |
| Tensão de alimentação | — | 5 V |
| Faixa de temperatura de operação | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Programming Method | — | Altera programming hardware with MAX+PLUS II / legacy tools |
| Manufacturer | — | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |