EP1810LI-25 vs EP1810LI-45 비교

다음의 상세 나란히 비교: EP1810LI-25 제조: Altera 및 EP1810LI-45 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810LI-25 EP1810LI-45
브랜드 Altera Rochester Electronics
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete 활성
재고 상태 In Stock In Stock
단가 (USD) $9.95 $64.10
Family Altera Classic EPLD Altera Classic
Device Type EPLD (Erasable Programmable Logic Device), UV-erasable / OTP —
Macrocells 48 48
Usable Gates 900 900
Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency 40 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
I/O Pins 48 —
Dedicated Inputs 12 —
Global Clock Inputs 4 —
Interconnect Programmable global and local buses —
패키지 68-pin PLCC (J68, J-Lead) 68-pin PLCC / PQCC68 (J-Lead)
JESD-30 Package Code S-PQCC-J68 —
Process Technology CMOS —
Operating Temperature (Industrial 'I' suffix) -40 C to +85 C —
Programming Mode EPROM/UV-erasable (windowed) and OTP —
Development Tool Altera MAX+PLUS II —
RoHS 상태 unknown [DATA_NEEDED: RoHS status]
Lead-Free Status unknown —
Product Type — EPLD (Erasable Programmable Logic Device)
Maximum User I/O — 64 inputs / 48 outputs
Pin-to-Pin Logic Delay (tPD) — 45 ns
Counter Frequency (fCNT) — up to 100 MHz
Setup Time (tSU) — [DATA_NEEDED: setup time]
Technology — CMOS, UV-erasable EPROM configuration
공급 전압 — 5 V
동작 온도 범위 — -40 C to +85 C (Industrial, 'I' suffix)
Logic Blocks — 12 LABs of 4 macrocells each
Configuration Memory — Non-volatile UV-erasable EPROM
Programming Method — Altera programming hardware with MAX+PLUS II / legacy tools
Manufacturer — Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line)

데이터시트 & 자료

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