EP1810LI-35 vs EP1810LC-35 Comparação
Comparação detalhada lado a lado de EP1810LI-35 por Altera e EP1810LC-35 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Última compraComparação de especificações
| Parâmetro | EP1810LI-35 | EP1810LC-35 |
|---|---|---|
| Marca | Altera | Rochester Electronics |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Última compra |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $78,05 | $49,20 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| Encapsulamento | 68-pin PLCC (J-Lead, plastic) | 68-pin PLCC (J-Lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | CMOS, UV-erasable EPROM |
| Tensão de alimentação | 5 V (TTL-compatible I/O) | — |
| Temperatura de operação | -40 C to +85 C (industrial, 'I' suffix) | 0C to +70C (commercial) |
| Tipo de montagem | Surface Mount (PLCC socket compatible) | Surface Mount (socketable) |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED] |
| Nível MSL | [DATA_NEEDED: MSL rating] | — |
| Series | — | Classic EP1810 |
| Equivalent Gates | — | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | — | 28.6 MHz |
| Propagation Delay (tpd) | — | 35 ns (max, '-35' speed grade) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| I/O Pins | — | [DATA_NEEDED: I/O count exact] |
| Configuration Method | — | UV-erase + EPROM programmer |
| Programmable Interconnect | — | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | — | MAX+PLUS II / A+PLUS |