EP1810LI-35 vs EP1810LC-45 Comparação
Comparação detalhada lado a lado de EP1810LI-35 por Altera e EP1810LC-45 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoleteComparação de especificações
| Parâmetro | EP1810LI-35 | EP1810LC-45 |
|---|---|---|
| Marca | Altera | Rochester Electronics |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $78,05 | $49,90 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| Encapsulamento | 68-pin PLCC (J-Lead, plastic) | 68-pin PLCC (J-lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | — |
| Tensão de alimentação | 5 V (TTL-compatible I/O) | — |
| Temperatura de operação | -40 C to +85 C (industrial, 'I' suffix) | 0 °C to +70 °C (commercial) |
| Tipo de montagem | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| Nível MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |