EP1810LI-35 vs EP1810LC-45 Comparaison
Comparaison détaillée côte à côte de EP1810LI-35 par Altera et EP1810LC-45 par Rochester Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoleteComparaison des spécifications
| Paramètre | EP1810LI-35 | EP1810LC-45 |
|---|---|---|
| Marque | Altera | Rochester Electronics |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $78,05 | $49,90 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| Boîtier | 68-pin PLCC (J-Lead, plastic) | 68-pin PLCC (J-lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | — |
| Tension d'alimentation | 5 V (TTL-compatible I/O) | — |
| Température de fonctionnement | -40 C to +85 C (industrial, 'I' suffix) | 0 °C to +70 °C (commercial) |
| Type de montage | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |