EP1C12Q240 vs EP1C12Q240C7N Comparação
Comparação detalhada lado a lado de EP1C12Q240 por Altera e EP1C12Q240C7N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1C12Q240 | EP1C12Q240C7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $25,60 | $22,80 |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Series | Cyclone | Cyclone I |
| Logic Elements | 12,060 LE | 12,060 |
| Logic Array Blocks | 1,206 LABs | — |
| Total RAM Bits | 239,616 bits | 239,616 bits |
| Number of User I/O | 173 | — |
| Encapsulamento | 240-BFQFP | 240-pin PQFP / BFQFP |
| Número de pinos | 240 | — |
| Core Supply Voltage | 1.5 V | — |
| Process Technology | 0.13-um all-layer copper SRAM process | 130 nm CMOS |
| Configuration Technology | SRAM-based, reconfigurable | — |
| JTAG Boundary-Scan | Supported | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Faixa de temperatura de operação | [DATA_NEEDED: Depends on ordering suffix - C for commercial temperature, I for industrial temperature] | — |
| Speed Grade | [DATA_NEEDED: Speed grade suffix not specified in base part number] | C7 (commercial, -7) |
| Lead-Free / RoHS Status | [DATA_NEEDED: Base ordering code does not include N suffix; N-suffix variants are lead-free] | — |
| Status do ciclo de vida | Obsolete - Cyclone I family | — |
| Family | — | Cyclone |
| Manufacturer | — | Intel (formerly Altera) |
| Configurable Logic Blocks (CLBs) | — | 12,060 |
| Embedded Memory Blocks | — | 52 M4K blocks (4 Kbit each) |
| Maximum User I/O | — | 173 |
| Core Voltage | — | 1.5 V |
| Internal Performance | — | 320.1 MHz |
| Temperatura de operação | — | 0C to +85C (commercial) |
| Package Body Size | — | 34.60 x 34.60 mm |
| Lead Pitch | — | 0.50 mm |
| Terminal Form | — | Gull wing |
| PLLs | — | 2 (dual-clock) |
| Configuration Method | — | SRAM, serial/parallel via external flash |