EP20K400GC655-2 vs EP20K400GC655-3V Comparação
Comparação detalhada lado a lado de EP20K400GC655-2 por Altera e EP20K400GC655-3V por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP20K400GC655-2 | EP20K400GC655-3V |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $80,00 | $160,00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20K | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212992 |
| Maximum Internal Frequency | 200 MHz | — |
| Speed Grade | -2 | -3V (commercial temperature, Vcc 1.8 V) |
| Process Technology | 0.22 µm CMOS | CMOS |
| Core Supply Voltage | 2.5 V | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | — |
| LVDS Support | Yes | — |
| PLLs | 4 | — |
| Contagem de pinos | 655 | — |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| Tipo de montagem | Through-Hole (CPGA) | Through Hole (CPGA) |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial / industrial / military grade] |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Manufacturer | — | Altera (now Intel) |
| Logic Elements | — | 16640 |
| Typical Gate Count | — | 400000 |
| Number of User I/O | — | 496 |
| Frequência máxima de clock | — | 714.2 MHz |
| Propagation Delay | — | 3.6 ns |
| Encapsulamento | — | 655-BCPGA (62.48 mm x 62.48 mm) |
| Package Equivalence Code | — | SPGA655, 47x47 |
| Peak Reflow Temperature | — | 220 C |
| Configuration | — | SRAM-based (requires EPC configuration device) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |