EP2A25F672I9N vs EP2A25F672I-9 Comparação
Comparação detalhada lado a lado de EP2A25F672I9N por Intel e EP2A25F672I-9 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP2A25F672I9N | EP2A25F672I-9 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $215,00 | $195,00 |
| Series | APEX II (EP2A25) | — |
| Family | APEX II | APEX II |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Logic Elements / Cells | 24,320 | — |
| System Gates | 900,000 (typical) | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm CMOS |
| Maximum Internal Frequency | 236 MHz | — |
| Propagation Delay (tpd) | 2.23 ns | — |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.525 V) | — |
| I/O Supply Voltage | [DATA_NEEDED: VCCIO range] | — |
| Encapsulamento | 672-pin FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Tipo de montagem | Surface Mount | Surface Mount (BGA) |
| Temperatura de operação | -40 °C to +85 °C (Industrial, 'I' suffix) | — |
| Speed Grade | 9 (fastest commercial APEX II) | -9 |
| Embedded System Blocks (ESB) | Yes (on-chip RAM/ROM) | — |
| PLLs | 4 | — |
| Configuration | JTAG / in-system programmable | — |
| Status RoHS | [DATA_NEEDED: confirmed] | [DATA_NEEDED: RoHS status] |
| Nível MSL | [DATA_NEEDED] | — |
| AEC-Q100 | not_applicable | — |
| Logic Elements (typical) | — | 25,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Nível de sensibilidade à umidade (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |