EP3SE50F484C2G vs EP3SE50F484C3G Comparação
Comparação detalhada lado a lado de EP3SE50F484C2G por Intel e EP3SE50F484C3G por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP3SE50F484C2G | EP3SE50F484C3G |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $1.180,00 | $205,00 |
| Series | Stratix III E | — |
| Number of Logic Elements / Cells | 47,500 | — |
| Number of LABs / CLBs | 1,900 | — |
| Total RAM Bits | 5,760,000 (5,760 Kbit) | — |
| Number of User I/O | 296 | — |
| Encapsulamento / Caixa | 484-BBGA, FCBGA (FineLine BGA) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Core Voltage Supply | 0.86 V to 1.15 V | — |
| Temperatura de operação | 0 °C to +85 °C (TJ) | 0C to +85C (commercial, "C") |
| Process Technology | 40 nm TSMC low-power CMOS | — |
| Logic Element Architecture | Adaptive Logic Module (ALM) with 8-input fracturable LUT | — |
| Embedded DSP Blocks | Yes (variable-precision multipliers) | — |
| Transceivers | Multi-gigabit transceivers (selected package pins) | — |
| Memory Interface Support | DDR / DDR2 / DDR3 with hard PHY | — |
| Partial Reconfiguration | Supported | — |
| Configuration Interface | JTAG, Passive Serial, Fast Passive Parallel | — |
| Part Status | Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy | — |
| Status RoHS | Compliant | Compliant (lead-free) |
| Family | — | Stratix III E |
| Logic Elements | — | 47,500 |
| Adaptive Logic Modules (ALMs) | — | 19,000 |
| Total Embedded Memory | — | 5,760,000 bits (5.76 Mbit) |
| M9K Memory Blocks | — | 320 (2,304 Kbits) |
| M144K Memory Blocks | — | 12 (1,728 Kbits) |
| User I/O Pins | — | 296 |
| 18x18 Multipliers | — | 384 |
| PLLs | — | 4 |
| Global Clock Networks | — | 16 |
| Encapsulamento | — | 484-ball FCBGA (F484), 1.0 mm pitch |
| Speed Grade | — | C3 |
| Process Node | — | 65 nm TSMC low-power |
| Core Voltage | — | 1.1 V |