EP610DC-35 vs EP610DC-30 Comparação

Comparação detalhada lado a lado de EP610DC-35 por Altera e EP610DC-30 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP610DC-35 EP610DC-30
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida NRND NRND
Status do estoque In Stock In Stock
Preço unitário (USD) $18,40 $10,40
Device Type CPLD - Classic EPLD —
Family Altera Classic EP610 EP610 (Classic Device Family)
Macrocells 16 16
Usable Gates 300 300
Propagation Delay (tPD) 35 ns 30 ns
Maximum Frequency (fMAX) 28.6 MHz —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V —
Process Technology CMOS —
Program/erase Method UV-erasable (windowed CERDIP) —
Encapsulamento 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CERDIP (windowed)
Tipo de montagem Through-Hole (DIP) Through-Hole
Temperatura de operação 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] Commercial (0C to +70C)
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) —
Status RoHS [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Logic Expanders — 4 (4 product terms per macrocell)
Maximum Pipelined Clock Frequency — 100 MHz
Dedicated Inputs — 16
I/O Pins — 16 (with output enable)
Speed Grade — -30 (30 ns tPD)
Technology — CMOS EPROM
Programmability — UV-erasable, windowed EPROM
Security Bit — Yes (protects design after programming)
Output Modes — Registered and Combinatorial

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