EP610IDC-10 vs EP610DC-30 Comparação

Comparação detalhada lado a lado de EP610IDC-10 por Intel e EP610DC-30 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP610IDC-10 EP610DC-30
Marca Intel Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete NRND
Status do estoque In Stock In Stock
Preço unitário (USD) $8,85 $10,40
Device Family Altera Classic EPLD —
Logic Capacity 300 usable gates —
Macrocell Count 16 macrocells —
Pin-to-Pin Logic Delay (tpd) 10 ns —
Maximum Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5 V (nominal) —
I/O Logic Compatibility 100% TTL emulation —
Technology CMOS, UV-erasable (windowed ceramic) CMOS EPROM
Package Type 24-pin Ceramic DIP (CDIP) —
Dedicated Inputs 4 16
I/O Pins 20 16 (with output enable)
Faixa de temperatura de operação 0 °C to +70 °C (commercial) —
Programmable Interconnect Yes (on-chip) —
In-System Programmability Yes (via MAX+PLUS II) —
Boundary-Scan Test Yes (per device documentation) —
Status RoHS [DATA_NEEDED: RoHS status of CDIP-10 variant] —
Tipo de montagem Through-hole Through-Hole
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP610 (Classic Device Family)
Macrocells — 16
Logic Expanders — 4 (4 product terms per macrocell)
Usable Gates — 300
Maximum Pipelined Clock Frequency — 100 MHz
Propagation Delay (tPD) — 30 ns
Encapsulamento — 24-pin CERDIP (windowed)
Speed Grade — -30 (30 ns tPD)
Programmability — UV-erasable, windowed EPROM
Security Bit — Yes (protects design after programming)
Output Modes — Registered and Combinatorial
Temperatura de operação — Commercial (0C to +70C)

Fichas técnicas e recursos

Ver todos os produtos Criar BOM Solicitar cotação