EP610LC-30 vs EP610DC-30 Comparação
Comparação detalhada lado a lado de EP610LC-30 por Intel e EP610DC-30 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP610LC-30 | EP610DC-30 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $16,40 | $10,40 |
| Family | Classic EPLD (EP610) | EP610 (Classic Device Family) |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| Encapsulamento | 24-pin CERDIP / PDIP | 24-pin CERDIP (windowed) |
| Temperatura de operação | 0 C to +70 C (commercial) / -55 C to +125 C (military) | Commercial (0C to +70C) |
| Erase/Program Cycles | 1000 typical | — |
| Tipo de montagem | Through-Hole | Through-Hole |
| Tipo de saída | CMOS tri-state (programmable) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |