EP610LC-30 vs EP610DC-30 비교
다음의 상세 나란히 비교: EP610LC-30 제조: Intel 및 EP610DC-30 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610LC-30 | EP610DC-30 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.40 | $10.40 |
| Family | Classic EPLD (EP610) | EP610 (Classic Device Family) |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| 패키지 | 24-pin CERDIP / PDIP | 24-pin CERDIP (windowed) |
| 동작 온도 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | Commercial (0C to +70C) |
| Erase/Program Cycles | 1000 typical | — |
| 실장 유형 | Through-Hole | Through-Hole |
| 출력 유형 | CMOS tri-state (programmable) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | — |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |