EP910LI-40 vs EP910LI-35T Comparação
Comparação detalhada lado a lado de EP910LI-40 por Altera e EP910LI-35T por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP910LI-40 | EP910LI-35T |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Última compra |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $12,90 | $28,50 |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 bidirectional | — |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Technology | Low-power CMOS (L-suffix) | CMOS, EPROM-based |
| Temperatura de operação | -40C to +85C (industrial, I-suffix) | -40C to +85C (industrial, 'I' suffix) |
| Encapsulamento | PLCC-44 (J-lead, windowed ceramic) | 44-pin PLCC (JEDEC) |
| Tipo de montagem | Surface Mount (socket-compatible) | Surface Mount / Socket |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| Status RoHS | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Classic EPLD (EP910) |
| Logic Elements | — | 24 macrocells |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | EPROM (UV-erasable for windowed versions) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |