EPC2LC20 vs EPC21LC20 Comparação
Comparação detalhada lado a lado de EPC2LC20 por Altera e EPC21LC20 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC2LC20 | EPC21LC20 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | Memory ICs | Memory ICs |
| Status do ciclo de vida | NRND | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,20 | $10,40 |
| Tipo de memória | Non-volatile configuration PROM | Serial Configuration PROM (Flash-based, in-system programmable) |
| Tamanho da memória | 1.6 Mbit | — |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | IEEE 1149.1 (JTAG) |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| Encapsulamento | 20-pin PLCC (J-lead, 9x9 mm) | — |
| Tipo de montagem | Surface Mount | Surface Mount (PLCC socket or solder) |
| Temperatura de operação | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | — |
| Status RoHS | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: confirm from Altera product page] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| Encapsulamento / Caixa | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Nível MSL | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |