EPC2LC20NUBAF48 vs EPC2LC20 Comparação
Comparação detalhada lado a lado de EPC2LC20NUBAF48 por Altera e EPC2LC20 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC2LC20NUBAF48 | EPC2LC20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | Memory ICs |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $16,40 | $7,20 |
| Tipo de memória | Non-volatile flash configuration PROM | Non-volatile configuration PROM |
| Memory Density | 2 Mbit (2,097,152 bits) | — |
| Core Supply Voltage (VCC) | 3.3 V (low-voltage 'L' variant) | — |
| I/O Logic Levels | 3.3 V LVCMOS (5V-tolerant inputs) | — |
| Configuration Interface | Altera serial (DATA, DCLK, nCS, ASDO) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| JTAG / ISP Support | IEEE 1532 / JTAG in-system programming | — |
| Cascade Support | Yes - dedicated nCASC pin for 2-device chains | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Programming Voltage | Internal 3.3V generation, no external VPP | — |
| FPGA Compatibility | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 | — |
| Encapsulamento | 20-pin Ultra FineLine BGA (UBGA, NU suffix) | 20-pin PLCC (J-lead, 9x9 mm) |
| Temperatura de operação | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Configuration Clock | Internal oscillator (DCLK output to FPGA) | — |
| Programming Tools | Quartus II Programmer, ByteBlaster II, USB-Blaster | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Tamanho da memória | — | 1.6 Mbit |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Tipo de montagem | — | Surface Mount |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |