EPM3128ATC100-10N vs EPM3128ATI100-5N Comparação
Comparação detalhada lado a lado de EPM3128ATC100-10N por Altera e EPM3128ATI100-5N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndIntel
EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera
EPM3128ATI100-5N ✓ AtivoComparação de especificações
| Parâmetro | EPM3128ATC100-10N | EPM3128ATI100-5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $5,20 | $11,45 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2500 | — |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | Non-volatile EEPROM |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| Encapsulamento | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-pin TQFP |
| Temperatura de operação | 0 °C to +70 °C (commercial) | -40C to +85C (Industrial) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | Compliant | Compliant (lead-free TQFP package) |
| Lead-Free | Yes | — |
| Nível MSL | 3 (per JEDEC J-STD-020) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells per LAB) |
| User I/O Pins | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs |
| Programming Method | — | In-System Programmable via IEEE Std. 1532 (JTAG) |
| JTAG Support | — | IEEE 1149.1 boundary scan |