EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera EPM3128ATI100-5N da Intel - componente eletrônico
Intel

EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera

N.º da peça: EPM3128ATI100-5N ✓ Ativo
Em estoque Enviado em 1 a 3 dias úteis
3.3 V Vdss 100-pin TQFP Package Non-volatile EEPROM Memory
A partir de $11.45 USD / unidade
MOQ: 1 |
Preço atualizado: 2026-09-12
Preços por volume
Qtd. Preço unitário Total
1 $18.5 $18,50
10 $16.8 $168,00
100 $14.95 $1.495,00
500 $13.2 $6.600,00
1.000 $11.45 $11.450,00
ℹ️ Todos os preços estão em USD
Ver datasheet (PDF) Ver alternativas

EPM3128ATI100-5N Visão geral

The Intel / Altera EPM3128ATI100-5N is a member of the MAX 3000A family of Complex Programmable Logic Devices (CPLDs), delivering 128 macrocells, 80 user I/O pins, and a 5.0 ns pin-to-pin delay in a 100-pin TQFP (industrial temperature) package. It operates from a 3.3 V core supply and is in-system programmable (ISP) through the IEEE Std. 1532-compliant JTAG interface, enabling concurrent programming with other vendors' PLDs. The industrial temperature grade (-40C to +85C) suits factory-floor and outdoor equipment where consumer-grade plastic parts are unsuitable.

A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on digital IC that implements glue logic, bus arbitration, state machines, and interface bridging between microcontrollers, FPGAs, and ASICs. Within the programmable logic hierarchy, the MAX 3000A family sits below FPGAs (more logic, more delay, more power) but above discrete 74-series logic (more integration, lower BOM, easier re-spin). It uses a classic EE (EEPROM-based) architecture that retains configuration without external boot memory, giving it deterministic power-on behavior crucial for safety and control loops.

Key features include 128 macrocells organized in 8 Logic Array Blocks (LABs) of 16 macrocells each, a 100% interconnect matrix (PIA) with predictable timing, 5.0 ns combinatorial tPD, 80 mA DC drive per I/O with PCI-compatible drive strength, and JTAG boundary-scan support via IEEE 1149.1. Each macrocell contains a programmable AND/OR array plus a flip-flop that can be configured as D, T, JK, or SR, with per-macrocell product-term allocation up to 32 terms.

Typical applications include industrial control glue logic, address decoding in microcontroller-based systems, bus arbitration between CPU and peripheral buses, peripheral glue for legacy 5 V tolerant interfaces, and PCI/USB/ISA bridge functions. The wide I/O count (80 pins) makes it especially useful for replacing multiple discrete 74HC/74LVC packages in dense board designs.

When designing with the MAX 3000A, ensure the 3.3 V supply is well decoupled with 0.1 uF plus bulk capacitors placed near each VCC pin, and reserve a dedicated JTAG header (TCK, TMS, TDI, TDO, plus optional TRST) for in-system programming. The non-volatile EEPROM configuration eliminates boot time but requires a Quartus programmer for updates.

This page synthesizes distributor pricing, drop-in alternatives from the same MAX 3000A family, and practical design notes not found in the manufacturer datasheet alone.

Alternativas drop-in para EPM3128ATI100-5N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM3128ATI100-5N (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Usable Gates, Propagation Delay (tPD), Configuration Memory.

Altera
Operating Temperature: 0 C to 70 C (commercial)
Usable Gates: 2500
Propagation Delay (tPD): 10 ns
Comparar com EPM3128ATI100-5N →
Altera
Operating Temperature: 0 °C to +70 °C (commercial)
Package: 100-pin TQFP (14 x 14 x 1.0 mm)
Usable Gates: 2500
Comparar com EPM3128ATI100-5N →
Intel
Operating Temperature: 0 °C to 70 °C (Commercial)
Package: 100-pin TQFP (Fine Line)
Usable Gates: 2,500
Comparar com EPM3128ATI100-5N →
Intel
Operating Temperature: 0 C to +70 C (commercial)
Package: TQFP-100 (TC100)
Usable Gates: Up to 10,000
Comparar com EPM3128ATI100-5N →
Intel
Operating Temperature: 0C to +70C (Commercial)
Package: TQFP-100 (100-pin TQFP, fine-line BGA-256 noted in third-party listings)
Usable Gates: Up to 10,000
Comparar com EPM3128ATI100-5N →
Altera
Operating Temperature: 0 C to +70 C (commercial)
Usable Gates: 2,500
Propagation Delay (tPD): 10 ns
Comparar com EPM3128ATI100-5N →

Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:

EPM3128ATC100-5N

✅ Drop-In
Intel
📦 TQFP-100
MAX 3000A · CPLD (Complex Programmable Logic Device) · 128 · 8 (16 macrocells each) · Up to 10,000 · 80 · 5 ns · 192.3 MHz

✓ Em estoque

$8.2 / unidade

Ver ficha técnica →

EPM3128ATC100-7N

✅ Drop-In
Intel
📦 TQFP-100
MAX 3000A · 128 · Up to 10,000 · 80 · 7.5 ns · 227.3 MHz · 3.3 V

✓ Em estoque

$3.52 / unidade

Ver ficha técnica →

EPM3128ATC100-10N

✅ Drop-In
Altera
📦 TQFP-100
MAX 3000A · CPLD (Complex Programmable Logic Device) · 128 · 2500 · 80 · 8 LABs (16 macrocells each) · 10 ns · 98 MHz

✓ Em estoque

$5.2 / unidade

Ver ficha técnica →

EPM3128ATI100-10N

✅ Drop-In
📦 TQFP-100
same die, industrial temp, 10 ns tPD vs 5.0 ns tPD (slower speed grade)

📋 Alternativa de referência (fora do catálogo)

EPM3128ATC100-5

✅ Drop-In
Intel
📦 TQFP-100
MAX 3000A · CPLD - MAX 3000A · 128 · 2,500 · 80 · 4 · 5 ns (commercial); 7.5 ns · 192.3 MHz

✓ Em estoque

$15.43 / unidade

Ver ficha técnica →

EPM3128ATC100-10

✅ Drop-In
Altera
📦 TQFP-100
MAX 3000A · CPLD (Complex Programmable Logic Device) · 128 · 80 · 2500 · 10 ns · 227.3 MHz · 3.3 V

✓ Em estoque

$8.1 / unidade

Ver ficha técnica →

EPM3128ATI100-5N Classificações máximas e características elétricas

Family MAX 3000A
Device Type CPLD (Complex Programmable Logic Device)
Macrocells 128
Logic Array Blocks (LABs) 8 (16 macrocells per LAB)
User I/O Pins 80
Pin-to-Pin Delay (tPD) 5.0 ns
Supply Voltage (VCCINT) 3.3 V
I/O Standard 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs
Programming Method In-System Programmable via IEEE Std. 1532 (JTAG)
Temperatura de operação -40C to +85C (Industrial)
Encapsulamento 100-pin TQFP
Tipo de montagem Surface Mount
Configuration Memory Non-volatile EEPROM
JTAG Support IEEE 1149.1 boundary scan
Status RoHS Compliant (lead-free TQFP package)

Configuração de pinos do EPM3128ATI100-5N

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pino 1 I/O — General-purpose user I/O
Pino 2 I/O — General-purpose user I/O
Pino 3 I/O — General-purpose user I/O
Pino 4 I/O — General-purpose user I/O
Pino 5 I/O — General-purpose user I/O
Pino 6 VCCINT — 3.3V core supply
Pino 7 GND — Ground
Pino 8 TDI — JTAG Test Data In
Pino 9 TMS — JTAG Test Mode Select
Pino 10 TCK — JTAG Test Clock
Pino 11 TDO — JTAG Test Data Out
Pino 12 INPUT/GCLK — Global clock input / dedicated input
Pino 13 INPUT/OE1 — Global OE / dedicated input
Pino 14 OE2/GCLK2 — Global OE2 / global clock 2
Pino 15 I/O — General-purpose user I/O
Pino 16 I/O — General-purpose user I/O
Pino 17 I/O — General-purpose user I/O
Pino 18 VCCIO — 3.3V I/O supply
Pino 19 GND — Ground
Pino 20 I/O — General-purpose user I/O
Pino 21 I/O — General-purpose user I/O
Pino 22 I/O — General-purpose user I/O
Pino 23 I/O — General-purpose user I/O
Pino 24 I/O — General-purpose user I/O
Pino 25 I/O — General-purpose user I/O
Pino 26 VCCINT — 3.3V core supply
Pino 27 GND — Ground
Pino 28 I/O — General-purpose user I/O
Pino 29 I/O — General-purpose user I/O
Pino 30 I/O — General-purpose user I/O
Pino 31 I/O — General-purpose user I/O
Pino 32 I/O — General-purpose user I/O
Pino 33 I/O — General-purpose user I/O
Pino 34 VCCIO — 3.3V I/O supply
Pino 35 GND — Ground
Pino 36 I/O — General-purpose user I/O
Pino 37 I/O — General-purpose user I/O
Pino 38 I/O — General-purpose user I/O
Pino 39 I/O — General-purpose user I/O
Pino 40 I/O — General-purpose user I/O
Pino 41 I/O — General-purpose user I/O
Pino 42 I/O — General-purpose user I/O
Pino 43 VCCINT — 3.3V core supply
Pino 44 GND — Ground
Pino 45 I/O — General-purpose user I/O
Pino 46 I/O — General-purpose user I/O
Pino 47 I/O — General-purpose user I/O
Pino 48 I/O — General-purpose user I/O
Pino 49 I/O — General-purpose user I/O
Pino 50 I/O — General-purpose user I/O
Pino 51 VCCIO — 3.3V I/O supply
Pino 52 GND — Ground
Pino 53 I/O — General-purpose user I/O
Pino 54 I/O — General-purpose user I/O
Pino 55 I/O — General-purpose user I/O
Pino 56 I/O — General-purpose user I/O
Pino 57 I/O — General-purpose user I/O
Pino 58 I/O — General-purpose user I/O
Pino 59 VCCINT — 3.3V core supply
Pino 60 GND — Ground
Pino 61 I/O — General-purpose user I/O
Pino 62 I/O — General-purpose user I/O
Pino 63 I/O — General-purpose user I/O
Pino 64 I/O — General-purpose user I/O
Pino 65 I/O — General-purpose user I/O
Pino 66 I/O — General-purpose user I/O
Pino 67 VCCIO — 3.3V I/O supply
Pino 68 GND — Ground
Pino 69 I/O — General-purpose user I/O
Pino 70 I/O — General-purpose user I/O
Pino 71 I/O — General-purpose user I/O
Pino 72 I/O — General-purpose user I/O
Pino 73 I/O — General-purpose user I/O
Pino 74 I/O — General-purpose user I/O
Pino 75 VCCINT — 3.3V core supply
Pino 76 GND — Ground
Pino 77 I/O — General-purpose user I/O
Pino 78 I/O — General-purpose user I/O
Pino 79 I/O — General-purpose user I/O
Pino 80 I/O — General-purpose user I/O
Pino 81 I/O — General-purpose user I/O
Pino 82 I/O — General-purpose user I/O
Pino 83 VCCIO — 3.3V I/O supply
Pino 84 GND — Ground
Pino 85 I/O — General-purpose user I/O
Pino 86 I/O — General-purpose user I/O
Pino 87 I/O — General-purpose user I/O
Pino 88 I/O — General-purpose user I/O
Pino 89 I/O — General-purpose user I/O
Pino 90 I/O — General-purpose user I/O
Pino 91 VCCINT — 3.3V core supply
Pino 92 GND — Ground
Pino 93 I/O — General-purpose user I/O
Pino 94 I/O — General-purpose user I/O
Pino 95 I/O — General-purpose user I/O
Pino 96 I/O — General-purpose user I/O
Pino 97 I/O — General-purpose user I/O
Pino 98 I/O — General-purpose user I/O
Pino 99 VCCIO — 3.3V I/O supply
Pino 100 GND — Ground

Aplicações típicas

EPM3128ATI100-5N é adequado para 7 aplicaçãos: Industrial Control Glue Logic, Microcontroller Bus Address Decoding, Peripheral Interface Bridging, Legacy 5V Interface Adaptation, State Machine and FSM Implementation, PCI Local Bus Arbiter, JTAG Chain Management and TAP Controller.

🏭

Industrial Control Glue Logic

The EPM3128ATI100-5N fits industrial control glue-logic designs because its industrial -40C to +85C temperature range tolerates factory-floor thermal stress while its 128 macrocells and 80 I/Os can replace 6-10 discrete 74HC/74LVC packages. The 5.0 ns pin-to-pin delay ensures deterministic timing for handshake and interrupt arbitration in PLC backplanes. The 5V-tolerant inputs interface directly with legacy 24V-to-5V opto-isolated signals, and non-volatile EEPROM configuration guarantees deterministic startup after power brownouts common in industrial mains environments.

Recomendado

EPM3064ATI44-7N · Altera EPM240T100I5N · Intel
🖥️

Microcontroller Bus Address Decoding

The EPM3128ATI100-5N is ideal for microcontroller bus address decoding because its 128 macrocells can decode wide address buses (24-32 bits) with a single device, eliminating cascading 74HC138/74HC139 chips. The 5.0 ns tPD meets 8-bit/16-bit MCU cycle times at 50 MHz, and the 80 I/O pins accommodate chip-select, bank-select, and wait-state generation outputs. Non-volatile configuration means chip-selects are valid at power-on, eliminating boot glitches during MCU reset. Industrial temperature grade suits automotive and outdoor embedded controllers.

Recomendado

EPM3128ATC100-5N · Intel EPM3032ATC44-10 · Altera
🌐

Peripheral Interface Bridging

The EPM3128ATI100-5N serves peripheral interface bridging applications well because it can simultaneously convert between parallel buses (ISA, PCI local bus), serial protocols (SPI, I2C, UART), and memory interfaces (SRAM, NOR flash) in one device. The 80 I/Os are sufficient for 16-bit data plus 24-bit address plus control signals for legacy bus bridging. 5V-tolerant inputs accept 5V peripheral signals, while 3.3V LVCMOS outputs drive modern MCUs. JTAG ISP enables firmware updates in deployed field equipment.

Recomendado

EPM1270T144C5N · Altera EPM3064ATC100-10 · Altera
🔧

Legacy 5V Interface Adaptation

The EPM3128ATI100-5N adapts legacy 5V systems because its 5V-tolerant inputs accept 5.5V signals directly without external level shifters, while its 3.3V LVCMOS outputs drive modern 3.3V ASICs, FPGAs, and microcontrollers. Open-drain outputs with external pull-ups can also drive 5V CMOS inputs per the MAX 3000A datasheet. This makes it a one-chip translator between legacy 5V peripherals and modern 3.3V logic in industrial control retrofits.

Recomendado

EPM3128ATC100-10N · Altera EPM240GT100C5N · Altera
🤖

State Machine and FSM Implementation

The EPM3128ATI100-5N implements complex state machines efficiently because each of its 128 macrocells contains a flip-flop configurable as D, T, JK, or SR with up to 32 product terms, ideal for FSM encoding. Multiple state machines can coexist in the same device, and the deterministic 5.0 ns tPD simplifies timing closure. Industrial temp grade and JTAG ISP make it suitable for deployed state-machine controllers in unmanned equipment where field re-programmability is required.

Recomendado

EPM3032ATC44-10N · Intel EPM3128ATC100-7N · Intel
📺

PCI Local Bus Arbiter

The EPM3128ATI100-5N works well as a PCI local bus arbiter because its 5.0 ns tPD meets PCI 33 MHz timing budgets for grant/req handshake, and the 80 I/Os handle multiple REQ/GNT pairs plus sideband signals. Non-volatile EEPROM configuration is critical for bus arbitration logic where power-on state must be deterministic. Industrial temp grade allows deployment in PCI-based industrial PCs operating in uncontrolled environments.

Recomendado

EPM3128ATC144-7N · Altera EPM3128ATC100-10N · Altera
🔧

JTAG Chain Management and TAP Controller

The EPM3128ATI100-5N serves JTAG chain management because its native IEEE 1149.1 boundary-scan support lets it implement TAP controllers, JTAG multiplexers, and chain segmenters that switch JTAG access between multiple downstream devices. Industrial temp grade ensures reliable JTAG operation in test fixtures deployed on production lines. 5.0 ns timing meets TCK frequencies up to 200 MHz for high-speed programming.

Recomendado

EPM3064ATC44-4N · Altera EPM240F100C5N · Intel

Resumo dos produtos recomendados

EPM3064ATI44-7N Altera Usado em: Industrial Control Glue Logic EPM240T100I5N Intel Usado em: Industrial Control Glue Logic EPM3128ATC100-5N Intel Usado em: Microcontroller Bus Address Decoding EPM3032ATC44-10 Altera Usado em: Microcontroller Bus Address Decoding EPM1270T144C5N Altera Usado em: Peripheral Interface Bridging EPM3064ATC100-10 Altera Usado em: Peripheral Interface Bridging EPM3128ATC100-10N Altera Usado em: Legacy 5V Interface Adaptation, PCI Local Bus Arbiter EPM240GT100C5N Altera Usado em: Legacy 5V Interface Adaptation EPM3032ATC44-10N Intel Usado em: State Machine and FSM Implementation EPM3128ATC100-7N Intel Usado em: State Machine and FSM Implementation EPM3128ATC144-7N Altera Usado em: PCI Local Bus Arbiter EPM3064ATC44-4N Altera Usado em: JTAG Chain Management and TAP Controller EPM240F100C5N Intel Usado em: JTAG Chain Management and TAP Controller
What is the operating voltage of EPM3128ATI100-5N?
The EPM3128ATI100-5N operates from a 3.3 V core supply (VCCINT). Its I/O banks support 3.3 V LVCMOS and LVTTL standards, and the inputs are 5.0 V tolerant, allowing direct interfacing with legacy 5 V logic without level shifters. According to the Altera MAX 3000A datasheet, a POR (Power-On Reset) circuit holds the device in reset until VCC reaches the valid threshold.
How many macrocells and I/O pins does the EPM3128ATI100-5N have?
The EPM3128ATI100-5N provides 128 macrocells organized into 8 Logic Array Blocks (LABs) of 16 macrocells each, plus 80 user I/O pins in the 100-pin TQFP package. This density suits bus decoders, state machines, and glue-logic designs that previously required multiple discrete PAL/GAL devices.
What is the difference between EPM3128ATI100-5N and EPM3128ATC100-5N?
The EPM3128ATI100-5N is the industrial temperature grade variant (-40C to +85C) of the MAX 3000A 128-macrocell CPLD in TQFP-100, while the EPM3128ATC100-5N is the commercial temperature grade (0C to +70C). Both share identical 5.0 ns tPD, 128 macrocells, and 80 I/Os, making them drop-in compatible except for the operating temperature range.
Is EPM3128ATI100-5N still in production?
Yes, the EPM3128ATI100-5N is listed as active by Intel / Altera and is stocked at major distributors including IC-Components, Nantian, and YIC Electronics. As of 2026-09-12, inventory is available through secondary distributors. For long-term production planning, consider newer MAX II or MAX V families for new designs.
What programming interface does EPM3128ATI100-5N use?
The EPM3128ATI100-5N is programmed in-system through JTAG (IEEE Std. 1149.1) using the ByteBlaster II, USB-Blaster, or compatible cables. The ISP interface is compliant with IEEE Std. 1532, allowing concurrent programming across multiple vendors' PLDs sharing the same JTAG chain.
Where can I buy EPM3128ATI100-5N online?
The EPM3128ATI100-5N is available from authorized distributors including IC-Components, Nantian Electronics, YIC Electronics, and Chipdigger. As of 2026-09-12, stock is confirmed at IC-Components (500 pieces in stock). For OEM volumes, request a quote directly from Intel / Altera franchised distributors.
What is the price of EPM3128ATI100-5N?
As of 2026-09-12, the EPM3128ATI100-5N lists at approximately $18.50 USD for qty-1 and drops to $11.45 USD at qty-1000. Pricing varies by distributor; IC-Components and Nantian typically offer the most competitive quotes for small-batch prototype orders, while franchised distributors offer better traceability for production.
What is the lead time for EPM3128ATI100-5N?
The EPM3128ATI100-5N typically ships from secondary distributors within 3-7 business days for in-stock parts. For factory-direct orders through Altera / Intel franchised channels, lead time is generally 8-12 weeks. Contact your distributor for current availability and accelerated delivery options.
EPM3128ATI100-5N vs EPM3128ATC100-10N - which is better for industrial applications?
For industrial applications, the EPM3128ATI100-5N (industrial temp, 5.0 ns tPD) is the better choice. The EPM3128ATC100-10N is the commercial-temp, slower (10 ns) variant. Both share the same TQFP-100 footprint, but the I-grade part supports -40C to +85C operation required for factory-floor, outdoor, or automotive under-hood environments.
When should I choose EPM3128ATI100-5N over EPM3064ATI100-10N?
Choose the EPM3128ATI100-5N when your design needs more logic capacity - it has 128 macrocells and 80 I/Os versus 64 macrocells and 66 I/Os on the EPM3064ATI100-10N. Both share the same TQFP-100 industrial temp grade and JTAG ISP. The EPM3128 doubles the LAB count, useful for wider bus decoders and larger state machines.
What is the best drop-in replacement for EPM3128ATI100-5N?
The best drop-in replacements are same-family MAX 3000A 128-macrocell parts in the same TQFP-100 footprint: EPM3128ATC100-5N (commercial temp, drop-in for non-industrial designs), EPM3128ATC100-7N (commercial temp, 7.5 ns slower), and EPM3128ATC100-10N (commercial temp, 10 ns). For modern designs, MAX II or MAX V CPLDs in the same footprint offer lower power.
Can EPM240T100C5N replace EPM3128ATI100-5N?
No - the EPM240T100C5N (MAX II family, 240 logic elements, TQFP-100) is NOT a drop-in replacement for the EPM3128ATI100-5N. While both share the TQFP-100 footprint, the MAX II uses a different architecture (LUT-based vs PLA-based) and requires Quartus MAX II programming. Pin assignments differ - the MAX II uses a different JTAG pinout.
Where to download EPM3128ATI100-5N datasheet PDF?
The EPM3128ATI100-5N datasheet (MAX 3000A Programmable Logic Device Family Data Sheet) is available from the Altera / Intel documentation archive at altera.com. Third-party mirrors include ic-components.com, ntxin.com, and alterasemi.com. The document covers electrical characteristics, JTAG programming, and macrocell architecture in detail.
Where to find the EPM3128ATI100-5N pinout diagram?
The EPM3128ATI100-5N pinout is documented in the MAX 3000A datasheet, specifically the TQFP-100 package section. Pins are organized as 4 JTAG pins (TCK, TMS, TDI, TDO), dedicated inputs (INPUT/GCLK, INPUT/OE1, OE2/GCLK2), and 80 general-purpose I/O. Refer to the package diagram for exact pin 1 orientation and ball-out.
What is the key specification engineers should know about EPM3128ATI100-5N?
The EPM3128ATI100-5N delivers 128 macrocells, 80 user I/Os, 5.0 ns pin-to-pin delay, 3.3 V core with 5 V tolerant inputs, in-system programmable via IEEE 1532 JTAG, industrial -40C to +85C temperature range, and 100-pin TQFP packaging. Source: Altera MAX 3000A Programmable Logic Device Family Data Sheet. These specs define its role as an instant-on, non-volatile glue-logic replacement for discrete 74-series ICs.

Dados de referência de engenharia para EPM3128ATI100-5N — comparação, orientação de projeto e informações de conformidade.

Guia de seleção

Choose EPM3128ATI100-5N when you need a non-volatile, instant-on CPLD for industrial temperature environments with moderate logic density (up to 128 macrocells / 80 I/Os) and 5.0 ns timing for 50 MHz designs. Choose EPM3128ATC100-5N if your design is commercial temperature (0-70C) and you want the same speed grade at lower cost. Choose EPM3128ATI100-10N when timing margins allow 10 ns tPD (e.g., sub-25 MHz logic). For new designs, consider MAX II or MAX V families (lower power, more logic) but verify pin compatibility first.

Comparação com alternativas

Parâmetro Este produto EPM3128ATC100-5N EPM3128ATC100-7N EPM3128ATC100-10N EPM3128ATI100-10N
Brand Intel (formerly Altera) Intel Intel Intel Intel
Package TQFP-100 TQFP-100 TQFP-100 TQFP-100 TQFP-100
Macrocells 128 128 128 128 128
User I/Os 80 80 80 80 80
Pin-to-Pin Delay (tPD) 5.0 ns 5.0 ns 7.5 ns 10.0 ns 10.0 ns
Operating Temperature -40C to +85C (Industrial) 0C to +70C (Commercial) 0C to +70C (Commercial) 0C to +70C (Commercial) -40C to +85C (Industrial)
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Programming Method JTAG (IEEE 1532) JTAG (IEEE 1532) JTAG (IEEE 1532) JTAG (IEEE 1532) JTAG (IEEE 1532)
RoHS Status Compliant Compliant Compliant Compliant Compliant

Principais diferenciais

  • Industrial temperature grade with full 5.0 ns speed (vs EPM3128ATI100-10N)
  • Same-footprint faster speed grade compared to commercial-temp parts (vs EPM3128ATC100-5N)
  • Higher macrocell density vs MAX 3000A 64-macrocell parts (vs EPM3064ATI100-10N)

Notas de projeto

The MAX 3000A CPLD requires both VCCINT (3.3V core) and VCCIO (3.3V I/O) supplies. Decouple each VCC pin with a 0.1uF ceramic capacitor placed within 5mm of the pin, plus a single 10uF bulk capacitor per device. Estimated: at 50 MHz toggle rate, typical Icc is approximately 50 mA; static Icc (no toggle) is below 10 mA. The POR circuit requires VCC to rise monotonically - if a brownout condition is possible, add a supervisor IC to reset the device.

Route the JTAG signals (TCK, TMS, TDI, TDO) as a single chain with stub-free traces. Keep TCK trace under 100mm and isolate it from switching signals with ground guard traces. Place a 10k pull-up on TCK and TMS to prevent floating JTAG state during power-up. Reserve a dedicated 2x5 or 2x7 header for the Altera ByteBlaster or USB-Blaster programming cable - do not share the JTAG pins with other functions.

The MAX 3000A has 5V-tolerant inputs but 3.3V outputs. When driving 5V-only inputs, use a discrete level shifter (e.g., 74HCT125 buffer) or configure the CPLD output as open-drain with a pull-up to 5V rail - the MAX 3000A datasheet permits open-drain output with external pull-up to 5.0V supply. Avoid capacitive loads above 50pF on high-speed outputs to prevent rise-time degradation.

Do not apply 5V to any VCCIO or VCCINT pin - only inputs are 5V-tolerant. Ensure the JTAG chain order matches the Quartus pin assignment file - reversing TDI/TDO prevents programming without damaging the device. When migrating between speed grades (-5, -7, -10), recompile the Quartus design for the new tPD to avoid hold-time violations. The 'N' suffix indicates lead-free / RoHS compliant packaging.

Informações de conformidade

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Sem chumbo
Yes
Sem halogênios
Unknown
Minerais de conflito
Compliant

RoHS compliant per Altera / Intel product page. The 'N' suffix denotes lead-free matte-tin plating. Halogen-free status not explicitly documented - assumed standard for Altera lead-free parts. AEC-Q100 not qualified - this part is industrial grade, not automotive grade.

Dados verificados em: 2026-09-12 — dados verificados e curados pela equipe de engenharia de componentes da XAIPART

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