EPM3128ATC144-7N vs EPM3128ATC144-10 Comparação
Comparação detalhada lado a lado de EPM3128ATC144-7N por Altera e EPM3128ATC144-10 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3128ATC144-7N | EPM3128ATC144-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,25 | $6,20 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | EEPROM-based, MAX architecture | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | Up to 10,000 | — |
| User I/Os | 96 | 96 |
| Contagem de pinos | 144 | — |
| Encapsulamento | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP (TQ144) |
| Logic Family | CMOS | — |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | 10 ns (speed grade -10) |
| Counter Frequency | Up to 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Temperatura de operação | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) | — |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 | — |
| Tipo de montagem | Surface Mount (SMD/SMT) | Surface Mount |
| Status RoHS | Lead-free (-7N suffix indicates Pb-free finish) | Compliant |
| Family | — | MAX 3000A |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 (typical) |
| Logic Elements / LABs | — | 4 Logic Array Blocks |
| Counter Frequency (fCNT) | — | Up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Interface | — | 1.5V / 1.8V / 2.5V / 3.3V |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| Lead-Free | — | Yes |