EPM3512AFI256-10N vs EPM3512AFI256-7 Comparação
Comparação detalhada lado a lado de EPM3512AFI256-10N por Altera e EPM3512AFI256-7 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Última compraComparação de especificações
| Parâmetro | EPM3512AFI256-10N | EPM3512AFI256-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $21,75 | $15,95 |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | 10,000 |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | IEEE Std. 1532 compliant via JTAG |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Encapsulamento | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch |
| Tipo de montagem | Surface Mount | Surface Mount (BGA) |
| Faixa de temperatura de operação | -40 °C to +85 °C (industrial) | — |
| Status RoHS | Compliant | [DATA_NEEDED: confirm from data] |
| Speed Grade | -10 (10 ns tPD) | — |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 32 (16 macrocells each) |
| User I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature (Industrial) | — | -40 °C to +85 °C |