EPM3512AFI256-10N vs EPM3512AFI256-7 Comparaison
Comparaison détaillée côte à côte de EPM3512AFI256-10N par Altera et EPM3512AFI256-7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512AFI256-10N | EPM3512AFI256-7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,75 | $15,95 |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | 10,000 |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | IEEE Std. 1532 compliant via JTAG |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Boîtier | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Plage de température de fonctionnement | -40 °C to +85 °C (industrial) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: confirm from data] |
| Speed Grade | -10 (10 ns tPD) | — |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 32 (16 macrocells each) |
| User I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature (Industrial) | — | -40 °C to +85 °C |