EPM5032DC-25 vs EPM5032JC25 Comparação

Comparação detalhada lado a lado de EPM5032DC-25 por Altera e EPM5032JC25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EPM5032DC-25 EPM5032JC25
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida NRND Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $3,55 $23,95
Manufacturer Altera (Intel Programmable Solutions Group) —
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 32 —
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Number of Dedicated Inputs 32 (in DIP-28 pinout) —
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) —
Encapsulamento CDIP-28 (Windowed Ceramic DIP-28) 28-pin PLCC (JC)
Process Technology CMOS, EPROM (UV-Erasable) —
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type macrocells with global Programmable Interconnect Array (PIA)
Output Structure Programmable I/O with output enable —
Flip-Flop Configuration D, T, JK, or SR (programmable) —
Temperatura de operação [DATA_NEEDED: operating temperature range] —
Status RoHS Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: RoHS status]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer —
Erasure Method UV light through ceramic window —
Family — MAX 5000
Device — EPM5032
Logic Elements — 32 macrocells
Propagation Delay (tPD) — 25 ns
Maximum Internal Frequency — 62.5 MHz
Product Terms — 320
Flip-Flops — 32
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Inputs to Array — 24
Número de saídas — 16
Technology — CMOS EPROM, UV-erasable (windowed) / OTP
Tensão de alimentação — 5 V (TTL-level I/O)
Tipo de montagem — Surface Mount

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