EPM5032DC-25 vs EPM5032JC25 Comparison

Detailed side-by-side comparison of EPM5032DC-25 by Altera and EPM5032JC25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC-25 EPM5032JC25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $3.55 $23.95
Manufacturer Altera (Intel Programmable Solutions Group) β€”
Product Family MAX 5000 β€”
Device Type UV Erasable Programmable Logic Device (EPLD) β€”
Macrocells 32 β€”
Pin-to-Pin Propagation Delay (tPD) 25 ns β€”
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] β€”
Setup Time (tSU) [DATA_NEEDED: setup time] β€”
Number of Dedicated Inputs 32 (in DIP-28 pinout) β€”
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) β€”
Package CDIP-28 (Windowed Ceramic DIP-28) 28-pin PLCC (JC)
Process Technology CMOS, EPROM (UV-Erasable) β€”
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type macrocells with global Programmable Interconnect Array (PIA)
Output Structure Programmable I/O with output enable β€”
Flip-Flop Configuration D, T, JK, or SR (programmable) β€”
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
RoHS Status Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: RoHS status]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer β€”
Erasure Method UV light through ceramic window β€”
Family β€” MAX 5000
Device β€” EPM5032
Logic Elements β€” 32 macrocells
Propagation Delay (tPD) β€” 25 ns
Maximum Internal Frequency β€” 62.5 MHz
Product Terms β€” 320
Flip-Flops β€” 32
Dedicated Inputs β€” 7
Bidirectional I/O Pins β€” 16
Total Inputs to Array β€” 24
Number of Outputs β€” 16
Technology β€” CMOS EPROM, UV-erasable (windowed) / OTP
Supply Voltage β€” 5 V (TTL-level I/O)
Mounting Type β€” Surface Mount

Datasheets & Resources

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