EPM5032DC20 vs EPM5032DI-20 Comparação
Comparação detalhada lado a lado de EPM5032DC20 por Altera e EPM5032DI-20 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5032DC20 | EPM5032DI-20 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,20 | $8,75 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 (bidirectional) | — |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | CMOS PAL-type EPLD with PIA |
| Process Technology | CMOS | — |
| Encapsulamento | 20-pin Ceramic DIP (DC) with UV window | Ceramic DIP-20 (windowed, UV-erasable) |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Tipo de montagem | Through-Hole (DIP) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Family | — | MAX 5000 (Altera legacy EPLD) |
| Bidirectional I/O Pins | — | 16 |
| Product Terms | — | 320 (maximum) |
| Flip-Flops | — | 16 (one per macrocell) |
| Frequência máxima de clock | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |