EPM5032DC20 vs EPM5032DI-20 Comparison
Detailed side-by-side comparison of EPM5032DC20 by Altera and EPM5032DI-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DC20 | EPM5032DI-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $8.75 |
| Device Family | MAX 5000 | β |
| Product Type | UV-erasable PLD (CPLD class) | β |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | β |
| Propagation Delay (tPD) | 20 ns | β |
| Maximum Frequency (Fmax) | 71.4 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 (bidirectional) | β |
| Total Inputs (max) | 24 | β |
| Output Macrocells | 16 | β |
| Clock Inputs | 1 (global) | β |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | CMOS PAL-type EPLD with PIA |
| Process Technology | CMOS | β |
| Package | 20-pin Ceramic DIP (DC) with UV window | Ceramic DIP-20 (windowed, UV-erasable) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Mounting Type | Through-Hole (DIP) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Family | β | MAX 5000 (Altera legacy EPLD) |
| Bidirectional I/O Pins | β | 16 |
| Product Terms | β | 320 (maximum) |
| Flip-Flops | β | 16 (one per macrocell) |
| Maximum Clock Frequency | β | 62.5 MHz |
| Pin-to-Pin Delay | β | 20 ns (speed grade -20) |
| Programming | β | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | β | Altera MAX+PLUS II (legacy) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |