EPM5032PC-15 vs EPM5032LC-15 Comparação
Comparação detalhada lado a lado de EPM5032PC-15 por Altera e EPM5032LC-15 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5032PC-15 | EPM5032LC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,10 | $8,20 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | — |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | — |
| Encapsulamento | 28-pin PDIP (PC suffix = windowed CerDIP) | JLCC-28 (windowed ceramic) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| Status RoHS | Non-compliant (CerDIP window, contains Be) | Non-compliant (contains Pb, ceramic-windowed package) |
| Lead-Free | No | — |
| Tipo de montagem | Through-Hole (DIP) | — |
| Family | — | MAX 5000 EPLD |
| Architecture | — | PAL-type AND/OR with PIA |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EPROM, 1.0 um process |
| Programmability | — | UV-Erasable / OTP |