EPM5032PC-15 vs EPM5032LC-15 비교
다음의 상세 나란히 비교: EPM5032PC-15 제조: Altera 및 EPM5032LC-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5032PC-15 | EPM5032LC-15 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $8.10 | $8.20 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | — |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | — |
| 패키지 | 28-pin PDIP (PC suffix = windowed CerDIP) | JLCC-28 (windowed ceramic) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | — |
| 동작 온도 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| RoHS 상태 | Non-compliant (CerDIP window, contains Be) | Non-compliant (contains Pb, ceramic-windowed package) |
| Lead-Free | No | — |
| 실장 유형 | Through-Hole (DIP) | — |
| Family | — | MAX 5000 EPLD |
| Architecture | — | PAL-type AND/OR with PIA |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EPROM, 1.0 um process |
| Programmability | — | UV-Erasable / OTP |