EPM5128GC-2 vs EPM5128GC2 Comparação

Comparação detalhada lado a lado de EPM5128GC-2 por Altera e EPM5128GC2 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EPM5128GC-2 EPM5128GC2
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $8,95 $54,00
Family MAX 5000 MAX 5000
Logic Elements / Gates 2,500 usable gates —
Macrocells 128 —
Number of Usable Gates 2,500 —
Maximum Operating Frequency 50 MHz —
Propagation Delay (tPD) Approx. 25 ns (typical, -2 speed grade) —
Supply Voltage (VCC) 5 V (nominal) —
Package Type 68-pin PGA (Pin Grid Array) —
Package Code (per Partstack) WPGA —
Number of Terminals 68 —
Programming Technology UV-erasable EPROM —
Temperatura de operação 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Grade (per Partstack) COMMERCIAL —
Terminal Form PIN/PEG —
Configuration Memory Non-volatile, one-time programmable (erasable via UV) On-chip EPROM (no external boot device)
Device Type — EPLD (Erasable Programmable Logic Device)
Macro Cells — 128
Usable Gates — 2.5K
Logic Array Blocks (LABs) — 8 (16 macro cells each)
Maximum Internal Frequency — 50 MHz
Supply Voltage VCC — 5 V
I/O Pins — 64
Dedicated Inputs — 16
Encapsulamento — Ceramic PGA (GC, windowed)
Programmable Flip-Flop Modes — D / T / JK / SR (selectable)
Architecture — AND/OR plane + programmable macro cell + PIA
Process Technology — CMOS EPROM
Reprogrammability — UV-erasable (windowed ceramic package)
Status RoHS — [DATA_NEEDED: RoHS status]
Contagem de pinos — [DATA_NEEDED: total PGA pin count]

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