EPM5192GI84 vs EPM5192GM-1 Comparação
Comparação detalhada lado a lado de EPM5192GI84 por Altera e EPM5192GM-1 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5192GI84 | EPM5192GM-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $19,80 | $27,80 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Encapsulamento | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) | CPGA-84 (Windowed Ceramic PGA) |
| Package Code | WPGA | — |
| Operating Voltage (VCC) | 5 V (typical) | — |
| I/O Logic Compatibility | TTL | — |
| Temperature Grade | Industrial | — |
| Programmable Flip-Flop Modes | D, T, JK, SR | — |
| Programmability | UV-erasable (windowed) / OTP | — |
| Programming File Format | JEDEC map via MAX+PLUS II / A+PLUS | — |
| Propagation Delay | [DATA_NEEDED: tPD in ns] | — |
| Max User I/O Pins | [DATA_NEEDED: usable I/O count for this package] | — |
| Faixa de temperatura de operação | -40 C to +85 C (industrial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Tipo de montagem | Through-Hole (PGA socket or PCB pin/peg) | Through-Hole (Pin Grid Array socket) |
| Status RoHS | [DATA_NEEDED: most legacy PGA parts are non-RoHS] | — |
| Lead-Free | [DATA_NEEDED: legacy part, likely contains lead] | — |
| Number of Terminals | 84 | — |
| Terminal Form | PIN/PEG | — |
| Package Shape | SQUARE | — |
| Logic Cells | — | 192 |
| Propagation Delay (tpd) | — | 55 ns |
| Process Technology | — | CMOS |
| Programmable Element | — | UV-erasable EPROM |
| Contagem de pinos | — | 84 |
| Tensão de alimentação | — | [DATA_NEEDED: VCC nominal] |
| Programmable Macrocells | — | 192 |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| RoHS Compliance | — | unknown (legacy ceramic PGA) |
| Lead-Free Status | — | unknown |
| Programming Interface | — | Altera ByteBlaster / JEDEC bitstream |
| Development Tool | — | Altera MAX+PLUS II (legacy) |